AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 30
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AT32UC3A464
Manufacturer Part Number
AT32UC3A464
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A464-CIUT
Manufacturer:
ATMEL
Quantity:
180
Part Number:
AT32UC3A464-CIUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A464-U
Manufacturer:
XILINX
Quantity:
1
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
3.9.1.6
3.9.1.7
3.9.1.8
32002F–03/2010
Bus Error Exception on Instruction Fetch
NMI Exception
INT3 Exception
caused the exception. The exception handler is responsible for performing the appropriate
action.
The Bus Error on Instruction Fetch exception is generated when the data bus detects an error
condition. This exception is caused by events related to the instruction stream. Therefore, exe-
cution can be restarted in a safe way after this exception, assuming that the condition that
caused the bus error is dealt with.
The NMI exception is generated when the NMI input line to the core is asserted. The NMI excep-
tion can not be masked by the SR[GM] bit. However, the core ignores the NMI input line when
processing an NMI Exception (the SR[M2:M0] bits are B’111). This guarantees serial execution
of NMI Exceptions, and simplifies the NMI hardware and software mechanisms.
Since the NMI exception is unrelated to the instruction stream, the instructions in the pipeline are
allowed to complete. After finishing the NMI exception routine, execution should continue at the
instruction following the last completed instruction in the instruction stream.
The INT3 exception is generated when the INT3 input line to the core is asserted. The INT3
exception can be masked by the SR[GM] bit, and the SR[I3M] bit. Hardware automatically sets
the SR[I3M] bit when accepting an INT3 exception, inhibiting new INT3 requests when process-
ing an INT3 request.
The INT3 Exception handler address is calculated by adding EVBA to an interrupt vector offset
specified by an interrupt controller outside the core. The interrupt controller is responsible for
providing the correct offset.
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x08;
BEAR = failing address
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x0C;
*(--SP
*(--SP
SR[M2:M0] = B’111;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x10;
SYS
SYS
SYS
SYS
SYS
SYS
) = PC of first non-issued instruction;
) = SR;
) = PC of first non-issued instruction;
) = SR;
) = PC of first noncompleted instruction;
) = SR;
AVR32
30