AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 57
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AT32UC3A464
Manufacturer Part Number
AT32UC3A464
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Quantity
Price
Company:
Part Number:
AT32UC3A464-CIUT
Manufacturer:
ATMEL
Quantity:
180
Part Number:
AT32UC3A464-CIUT
Manufacturer:
ATMEL/爱特梅尔
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20 000
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Part Number:
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XILINX
Quantity:
1
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 57 of 377
- Download datasheet (5Mb)
7. Performance counters
7.1
7.2
7.2.1
7.2.2
7.2.3
32000D–04/2011
Overview
Registers
Performance clock counter - PCCNT
Performance counter 0,1 - PCNT0, PCNT1
Performance counter control register - PCCR
A set of performance counters let users evaluate the performance of the system. This is useful
when scheduling code and performing optimizations. Two configurable event counters are pro-
vided in addition to a clock cycle counter. These three counters can be used to collect
information about for example cache miss rates, branch prediction hit rate and data hazard stall
cycles.
The three counters are implemented as 32-bit registers accessible through the system register
interface. They can be configured to issue an interrupt request in case of overflow, allowing a
software overflow counter to be implemented.
A performance counter control register is implemented in addition to the three counter registers.
This register controls which events to record in the counter, counter overflow interrupt enable
and other configuration data.
This register counts CPU clock cycles. When it reaches 0xFFFF_FFFF, it rolls over. The over-
flow flag is set and an exception is generated if configured by PCCR. The register can be reset
by writing to the C bit in PCCR. PCCNT can be preset to a value by writing directly to it. PCCNT
is written to zero upon reset.
These counters monitor events as configured by PCCR. When they reach 0xFFFF_FFFF, they
roll over. The overflow flag is set and an exception is generated if configured by PCCR. The reg-
isters can be reset by writing the R bit in PCCR. The registers can be preset to a value by writing
directly to them. PCNT0 and PCNT1 are written to zero upon reset.
This register controls the behaviour of the entire performance counter system, see
page
zero upon reset.
Figure 7-1.
31
57. This register is read and written by the mtsr and mfsr instructions. PCCR is written to
-
Performance counter control register
24
23
CONF1
18
17
CONF0
12
-
10
F
8
-
6
IE
4
Figure 7-1 on
AVR32
3
S
2
C
1
R
0
E
57
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