AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 93
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AT32UC3B0256
Manufacturer Part Number
AT32UC3B0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0256-A2UT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
AT32UC3B0256-U
Manufacturer:
ATMEL
Quantity:
543
Part Number:
AT32UC3B0256-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3B0256-Z2UT
Manufacturer:
ATMEL
Quantity:
444
9.2.4
32002F–03/2010
Entry into Debug Mode
Any instruction valid in Monitor Mode is also valid in OCD Mode. Memory operations can be con-
ducted without any special synchronization with external hardware.
All OCD units can be configured while the CPU executes in OCD Mode, but the following debug
features are disabled:
OCD Mode is exited by writing the retd instruction to DINST.
Figure 9-3.
Debug Mode can only be entered when the OCD is enabled, and Debug Mode is not masked.
The following ways of entry are then possible:
The debugger can identify the condition which caused entry into Debug Mode by examining the
status bits in the Development Status register (DS). Each cause of entry has a particular bit
associated with it. Several exceptions can trigger simultaneously, causing more than one bit to
be set.
Note that any privileged CPU mode may write the SR:D bit to one directly, but this will not cause
entry to Debug Mode.
• PC breakpoints
• Data breakpoints
• Watchpoints
• Program Trace
• Data Trace
• Debug request from the debugger
• Program counter breakpoint
• Data address or value breakpoint
• breakpoint instruction
• Trapping opcode 0x0000
• Single step
• Event on EVTI pin
• Abort command from the debugger
OCD
Instructions
mov r12,r7
sub r12,0x01
mov r6,r12
adc r6,r12,r7
retd
Executing instructions on the CPU in OCD Mode.
Opcode
0x0E9C
0x201C
0x1896
0xF807 0046
0xD623
Written by
tool to DINST
0x0E9C201C
0x0046D623
0x1896F807
Changes in DS
INC→0→1
INC→0→1
INC→0→1
DBS→0
AVR32
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