AT32UC3B164 Atmel Corporation, AT32UC3B164 Datasheet - Page 517

• Manufacturer Part Number: AT32UC3B164
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B164

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.6.2
24.6.2.1
Figure 24-3. Functional View of the Channel Block Diagram
24.6.2.2
32059L–AVR32–01/2012
PWM Channel
Block Diagram
Waveform Properties
Inputs from
Inputs from
Peripheral
generator
clock
Bus
divided clocks.
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the Mode reg-
ister (MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field
value in the Mode register (MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the Mode register are
cleared. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
tion is also true when the PWM master clock is turned off through the Power Manager .
Each of the
The different properties of output waveforms are:
• A clock selector which selects one of the clocks provided by the clock generator described in
• An internal counter clocked by the output of the clock selector. This internal counter is
• A comparator used to generate events according to the internal counter value. It also
• the internal clock selection. The internal channel counter is clocked by one of the clocks
Selector
Channel
Section
incremented or decremented according to the channel configuration and comparators
events. The size of the internal counter is
computes the PWMx output waveform according to the configuration.
provided by the clock generator described in the previous section. This channel parameter is
defined in the CPRE field of the CMRx register. This field is reset at 0.
Clock
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
F
clkB
CLK_PWM
CLK_PWM
24.6.1.
7
channels is composed of three blocks:
/8, F
/512, F
CLK_PWM
Counter
Internal
CLK_PWM
/16, F
/1024
CLK_PWM
/32, F
Comparator
20
bits.
CLK_PWM
CLK_PWM
/64, F
CLK_PWM
, F
CLK_PWM
/128, F
PWMx output
waveform
/2, F
CLK_PWM
CLK_PWM
/256,
/4,
517