AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 117
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AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- Current page: 117 of 377
- Download datasheet (5Mb)
Table 9-10.
9.3.9.3
Table 9-11.
9.3.10
Table 9-12.
32000D–04/2011
stswp.h
stswp.w
xchg
Mnemonics
ldm
ldmts
popm
pushm
stm
stmts
Mnemonics
breakpoint
cache
csrf
csrfcz
frs
mfdr
mfsr
mtdr
mtsr
musfr
mustr
System/Control
Multiple data
Load/Store Operations (Continued)
Mutiple data
System/Control
E
E
E
E
E
C
C
E
E
C
E
C
C
C
E
E
E
E
C
C
Rp[disp], Rs
Rd, Rx, Ry
Operands / Syntax
Rp{++}, Reglist16
{, R12={-1,0,1}}
Rp{++}, Reglist16
Reglist8 {, R12={-
1,0,1}}
Reglist8
{--}Rp, Reglist16
{--}Rp, Reglist16
Operands / Syntax
Rp[disp], Op
bp
bp
frs
Rd,
DebugRegAddress
Rd, SysRegNo
DebugRegAddress,
Rs
SysRegNo, Rs
Rs
Rd
Swap bytes and store halfword with
displacement.
Swap bytes and store word with
displacement.
Exchange register and memory
Description
Load multiple registers. R12 is tested if PC
is loaded.
Load multiple registers in application
context for task switch.
Pop multiple registers from stack. R12 is
tested if PC is popped.
Push multiple registers to stack.
Store multiple registers.
Store multiple registers in application
context for task switch.
Description
Breakpoint.
Perform cache operation
Clear status register flag.
Copy status register flag to C and Z.
Invalidates the return address stack
Move debug register to Rd.
Move system register to Rd.
Move Rs to debug register.
Move Rs to system register.
Move Rs to status register
Move status register to Rd
Operation
See Instruction Set Reference
See Instruction Set Reference
SR[bp5] ← 0
C ← SR[bp5]
Z ← SR[bp5]
See Instruction Set Reference
Rd ←DebugRegister[DebugRegAddr]
Rd ← SystemRegister[SysRegNo]
DebugRegister[DebugRegAddr] ← Rs
SystemRegister[SysRegNo] ← Rs
SR[3:0] ← Rs[3:0]
Rd ← ZE(SR[3:0])
Temp ← Rs[7:0], Rs[15:8]
*(Rp+(SE(disp12) << 1) ← Temp
Temp[31:24] ← Rs[7:0],
Temp[23:16] ← Rs[15:8],
Temp[15:8] ← Rs[23:16],
Temp[7:0] ← Rs[31:24]
*(Rp+(SE(disp12) << 2) ← Temp
See Instruction Set Reference
Operation
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
AVR32
1
1
1
Rev
1
1
1
1
1
1
117
Rev
1
1
1
1
1
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1
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