AT32UC3C0512C Atmel Corporation, AT32UC3C0512C Datasheet - Page 896
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AT32UC3C0512C
Manufacturer Part Number
AT32UC3C0512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512C
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
32117C–AVR-08/11
Table 32-7.
Table 32-8.
Table 32-9.
This field can be cleared by software. To avoid read-modify-write issues, the user should: freeze
the pipe, wait until the UPSTAX.PFREEZE is one, clear the PERSTA field in memory, and then
unfreeze the pipe.
31:24
23:21
ERCNT
• The control and status fields for the pipe and bank (Pn_CTR_STA_BK0/1):
• The control and status 1 of endpoint n (Pn_CTR_STA1):
31:19
-
-
– UNDERF: Underflow status for isochronous/Interrupt IN transfers. This status bit is
– OVERF: Overflow status for isochronous/interrupt OUT transfers. This status bit is
– CRCERR: CRC error status for isochronous IN transfers. See
– PERSTA: Pipe Error Status. See
–
–
– PDADDR: Should be set by the user. Device address for this pipe.
– ERCNT: Pipe Error Counter.
– CRC16ER: Is set if a CRC16 error occurs during an isochronous IN transaction.
– TOUTER: Is set if a Time-out error occurs during a USB transaction.
– PIDER: Is set if a PID error occurs during a USB transaction.
– DAPIDER: Is set if a Data PID error occurs during a USB transaction.
set by hardware at the current bank (where the IN packet should have been stored).
When a new successful transaction occurs this bit is overwritten to zero if
UPSTAX.ERRORFI has previously been cleared by software. See
on page
set by hardware at the current bank (where the OUT packet should have been
loaded). When a new successful transaction occurs this bit is overwritten to zero if
UPSTAX.ERRORFI has previously been cleared by software. See
on page
900.
PERMAX
page
PEPNUM
18
23:16
UNDERF
896) is larger than PERMAX, the UPSTAX.PERRI bit is set.
Status
20
CRC16ER
Pn_CTR_STA_BK0/1 structure
Pn_CTR_STA1 structure
PERSTA structure
: Should be set by the user. If the Pipe Error Counter (see
: Should be set by the user. Endpoint number for this pipe.
900.
900.
PERSTA
Status
17
OVERF
19
TOUTER
16
CRCERR
15:12
PERMAX
18
PIDER
“PERSTA structure”
11:8
15:0
PEPNUM
17
DAPIDER
Control
7
table.
Control
-
16
DTGLER
-
6:0
PDADDR
”CRC error” on page
”Data flow error”
”Data flow error”
Figure 32-9 on
AT32UC3C
896
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