AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 63

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.4.3
32002F–03/2010
EX stage local bus interface
access to the RAMs when the current owner voluntarily releases the RAMs, or after the
SPL/CPL timeout period, whichever comes first.
If the CPU wins arbitration for the RAMs, the CPU is guaranteed to own the RAM for the period
specified by the COP field in CPUCR. Any slave request will be left pending during this period,
even if the CPU is not using the RAMs.
The following state diagram shows the states in arbitration for the RAM.
Figure 6-2.
The state transitions are as follows:
Any CPU access to the the LOCAL section is completed in a single clock cycle, both for reads
and writes. Transfers on this bus can not be stalled. The CPU will never be stalled due to an
access to the LOCAL section. Accesses to this section is performed using regular load-store
instructions such as for example ldswp.w, ld.w, ld.ub, st.w, stswp.w, ldm or stm.
Which devices are mapped in the LOCAL section, and their memory maps, is device-specific.
The LOCAL interface must be enabled by the user by programming the LOCEN bit in CPUCR.
Accesses to LOCAL memory addresses without first enabling the section will result in a BUS
ERROR exception.
If the MPU is enabled, accesses to LOCAL will be subject to permission checking.
To ensure maximum transfer speed and cycle determinism, any slaves being addressed by the
CPU on the local bus must be able to receive and transmit data on the bus at CPU clock speeds.
The consequences of this may vary between different slave devices, but for some slave devices
it may imply that the slaves have to run at the CPU clock frequency when local bus transfers are
1: CPU_wants_to_perform_mem_access
2: CPU_access_complete && (been_in_state > CPUCR[COP])
3: (been_in_state > CPUCR[COP]) && slave_wants_to_perform_mem_access &&
(slave_been_pending > CPUCR[SPL])
4: CPU_wants_to_perform_mem_access && (CPU_been_pending > CPUCR[CPL])
5: slave_wants_to_perform_mem_access && !CPU_wants_to_perform_mem_access
6: slave_access_complete
CPU owns the RAM
Arbitration between CPU and slave interface for RAMs.
1
2
RAM is free
3
4
6
Slave I/F owns the RAM
5
AVR32
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