AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet
AT32UC3L0256
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AT32UC3L0256 Summary of contents
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... Independent Baudrate Generator, Support for SPI – Support for Hardware Handshaking • One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals – SPI Slaves can be Addressed ® ® AVR Microcontroller 32-bit Atmel AVR Microcontroller AT32UC3L0256 AT32UC3L0128 Summary 32145AS–12/2011 ...
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Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I • One 8-channel Analog-to-digital Converter (ADC) with Bits Resolution – Internal Temperature Sensor • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) ...
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Description The Atmel the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 high-per- formance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, ...
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The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing known reference clock. The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde- pendently programmed to perform frequency measurement, event ...
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Overview 2.1 Block Diagram Figure 2-1. RESET_N PA PB 32145AS–12/2011 Block Diagram MCKO MDO[5..0] MSEO[1..0] EVTI_N NEXUS EVTO_N CLASS 2+ TCK MEMORY PROTECTION UNIT JTAG OCD TDO INTERFACE TDI INSTR TMS INTERFACE DATAOUT aWire M M HIGH SPEED S/M ...
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... Capacitive Touch Module JTAG aWire Max Frequency Packages 32145AS–12/2011 Configuration Summary AT32UC3L0256 256KB Digital Frequency Locked Loop 20-150 MHz (DFLL) Phase Locked Loop 40-240 MHz (PLL) Crystal Oscillator 0.45-16 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115 kHz (RCSYS) ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32145AS–12/2011 TQFP48/QFN48 Pinout ...
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Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral ...
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Table 3-1. GPIO Controller Function Multiplexing High- 13 PA02 2 VDDIO drive I/O Normal 4 PA03 3 VDDIO I/O Normal 28 PA04 4 VDDIO I/O Normal 12 PA05 5 VDDIO I/O (TWI) High- drive I/O, 10 PA06 6 VDDIO 5V ...
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Table 3-1. GPIO Controller Function Multiplexing Normal 8 PB03 35 VDDIO I/O Normal I/O (TWI, 21 PB04 36 VDDIN 5V tolerant, SMBus) Normal I/O (TWI, 20 PB05 37 VDDIN 5V tolerant, SMBus) Normal 30 PB06 38 VDDIO I/O Normal 31 ...
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Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the ...
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Table 3-4. Pin EVTO_N MCKO MSEO[1] MSEO[0] 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for ...
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Signal Descriptions The following table gives details on signal names classified by peripheral. Table 3-7. Signal Descriptions List Signal Name Function ACAN3 - ACAN0 Negative inputs for comparators "A" ACAP3 - ACAP0 Positive inputs for comparators "A" ACBN3 - ...
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Table 3-7. Signal Descriptions List TMS Test Mode Select RESET_N Reset PWMA35 - PWMA0 PWMA channel waveforms PWMAOD35 - PWMA channel waveforms, open drain PWMAOD0 mode GCLK9 - GCLK0 Generic Clock Output GCLK_IN2 - GCLK_IN0 Generic Clock Input RC32OUT RC32K ...
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Table 3-7. Signal Descriptions List TWD Two-wire Serial Data Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data TXD Transmit Data Note: 1. ADCIFB: AD3 does ...
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I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up ...
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RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be ...
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... Memories 4.1 Embedded Memories • Internal high-speed Flash – 256Kbytes (AT32UC3L0256) – 128Kbytes (AT32UC3L0128) • Internal high-speed SRAM, single-cycle access at full speed – 32Kbytes 4.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even during boot ...
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Peripheral Address Map Table 4-3. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE0400 0xFFFE0800 0xFFFF0000 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 32145AS–12/2011 Peripheral Name FLASHCDW Flash Controller - FLASHCDW HMATRIX HSB Matrix - ...
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Table 4-3. Peripheral Address Mapping 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 4.4 4.5 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to ...
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The following GPIO registers are mapped on the local bus: Table 4-4. Port 0 1 32145AS–12/2011 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) ...
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Supply and Startup Considerations 5.1 Supply Considerations 5.1.1 Power Supplies The AT32UC3L0128/256 has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is ...
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Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). ...
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V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8 V supply as shown in same power (VDDIN = VDDIO = VDDCORE). Figure ...
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Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in use Shutdown mode. Figure 5-4. 1.98-3.6V ...
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Power-up Sequence 5.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this chapter. 5.1.4.2 Minimum Rise ...
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Programming and Debugging 6.1 Overview The AT32UC3L0128/256 supports programming and debugging through two interfaces, JTAG or aWire. JTAG is an industry standard interface and allows boundary scan for PCB testing, as well as daisy-chaining of multiple devices on the ...
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Table 6-1. Memory Service Reserved 6.2.2 SAB Security Restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below. 6.2.2.1 Security measure and control location A ...
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Table 6-4. OCD DCCPU, OCD DCEMU, OCD DCSR User page Other accesses Table 6-5. OCD DCCPU, OCD DCEMU, OCD DCSR User page FLASHCDW PB interface FLASH pages outside BOOTPROT Other accesses 32145AS–12/2011 Security Bit SAB Restrictions Name Address start 0x100000110 ...
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Electrical Characteristics 7.1 Absolute Maximum Ratings* Table 7-1. Absolute Maximum Ratings Operating temperature..................................... -40°C to +85°C Storage temperature...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0. (1) Voltage on ...
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Table 7-3. Symbol V VDDIO V VDDIN V VDDCORE V VDDANA Note: 7.3 Maximum Clock Frequencies These parameters are given in the following conditions: • V VDDCORE • Temperature = -40°C to 85°C Table 7-4. Symbol f CPU f PBA ...
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V – V – Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations section for more details • Operating conditions, external core supply – V – Corresponds to the ...
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Table 7-5. Power Consumption for Different Operating Modes Mode Conditions CPU running a recursive Fibonacci algorithm (1) Active CPU running a division algorithm (1) Idle (1) Frozen (1) Standby Stop DeepStop -OSC32K and AST stopped -Internal core supply -OSC32K running ...
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Figure 7-2. 32145AS–12/2011 Measurement Schematic, External Core Supply VDDIN Amp0 VDDIO VDDCORE VDDANA AT32UC3L0128/256 34 ...
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I/O Pin Characteristics Table 7-6. Normal I/O Pin Characteristics Symbol Parameter R Pull-up resistance PULLUP V Input low-level voltage IL V Input high-level voltage IH V Output low-level voltage OL V Output high-level voltage OH (2) f Output frequency ...
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Table 7-7. High-drive I/O Pin Characteristics Symbol Parameter R Pull-up resistance PULLUP V Input low-level voltage IL V Input high-level voltage IH V Output low-level voltage OL V Output high-level voltage OH Output frequency, all High-drive I/O f MAX pins, ...
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These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. Table 7-8. High-drive I/O, 5V Tolerant, Pin Characteristics Symbol Parameter ...
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Table 7-9. TWI Pin Characteristics Symbol Parameter V Output low-level voltage OL I Input leakage current LEAK I Input low leakage IL I Input high leakage IH C Input capacitance IN t Fall time FALL f Max frequency MAX Note: ...
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The capacitance of the external capacitors (C then be computed as follows: where C Table 7-11. Crystal Oscillator Characteristics Symbol Parameter f Crystal oscillator frequency OUT C Crystal ...
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Table 7-12. 32 KHz Crystal Oscillator Characteristics Symbol Parameter f Crystal oscillator frequency OUT t Startup time STARTUP C Crystal load capacitance L Internal equivalent load C i capacitance I Current consumption OSC32 R Equivalent series resistance S Notes: 1. ...
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Digital Frequency Locked Loop (DFLL) Characteristics Table 7-14. Digital Frequency Locked Loop Characteristics Symbol Parameter (2) f Output frequency OUT f Reference frequency REF FINE resolution step Frequency drift over voltage and temperature (2) Accuracy I Power consumption DFLL ...
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Figure 7-4. DFLL Open Loop Frequency Variation 160 150 140 130 120 110 100 90 80 -40 -20 Notes: 1. The plot shows a typical open loop mode behavior with COARSE= 99 and FINE= 255 2. These values are based ...
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RC Oscillator (RC32K) Characteristics Table 7-16. 32kHz RC Oscillator Characteristics Symbol Parameter (1) f Output frequency OUT I Current consumption RC32K (1) t Startup time STARTUP Note: 1. These values are based on simulation and characterization of other ...
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Table 7-20. Flash Endurance and Data Retention Symbol Parameter N Array endurance (write/page) FARRAY N General Purpose fuses endurance (write/bit) FFUSE t Data retention RET 7.8 Analog Characteristics 7.8.1 Voltage Regulator Characteristics Table 7-21. VREG Electrical Characteristics Symbol Parameter V ...
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Power-on Reset 18 Characteristics Table 7-23. POR18 Characteristics Symbol Parameter V Voltage threshold on V POT+ V Voltage threshold on V POT- (1) t Detection time DET I Current consumption POR18 (1) t Startup time STARTUP Note: 1. These ...
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Power-on Reset 33 Characteristics Table 7-24. POR33 Characteristics Symbol Parameter V Voltage threshold on V POT+ V Voltage threshold on V POT- (1) t Detection time DET I Current consumption POR33 (1) t Startup time STARTUP Note: 1. These ...
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Brown Out Detector Characteristics The values in Fuse register. Table 7-25. BODLEVEL Value 011111 binary (31) 0x1F 100111 binary (39) 0x27 Table 7-26. BOD Characteristics Symbol Parameter V BOD hysteresis HYST t Detection time DET I Current consumption BOD ...
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Analog to Digital Converter Characteristics Table 7-28. ADC Characteristics Symbol Parameter f ADC clock frequency ADC f ADC clock frequency ADC t Startup time STARTUP t Conversion time (latency) CONV Throughput rate Throughput rate V Reference voltage range ADVREFP ...
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Figure 7- The minimum sample and hold time (in ns) can be found using this formula: t SAMPLEHOLD Where n is the number of bits in the conversion. ADCIFB ACR register. Please refer to the ADCIFB chapter for ...
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Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. Table 7-32. Transfer Characteristics, 8-bit Resolution Mode Parameter Resolution ...
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Analog Comparator Characteristics Table 7-34. Analog Comparator Characteristics Symbol Parameter Condition Positive input (3) voltage range Negative input (3) voltage range V f (3) AC Statistical offset filter length = 2, hysteresis = 0 Clock frequency for f (3) ...
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Strong Pull-up Pull-down Table 7-36. Strong Pull-up Pull-down Parameter Pull-down resistor Pull-up resistor 7.8.10 USB Transceiver Characteristics The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be ...
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Timing Characteristics 7.9.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula CONST Where clock source other than RCSYS is selected as the CPU clock, the oscillator startup ...
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USART in SPI Mode Timing 7.9.3.1 Master mode Figure 7-8. SPCK MISO MOSI Figure 7-9. SPCK MISO MOSI Table 7-40. USART in SPI Mode Timing, Master Mode Symbol Parameter USPI0 MISO setup time before SPCK rises USPI1 MISO hold ...
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Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: Where the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. ...
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Figure 7-11. USART in SPI Slave Mode with (CPOL= CPHA (CPOL= CPHA= 1) SPCK MISO MOSI Figure 7-12. USART in SPI Slave Mode, NPCS Timing SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 7-41. USART in SPI mode Timing, Slave ...
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Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: Where on CPOL and NCPHA. chapter for a description of this clock. Maximum SPI Frequency, Slave Output Mode The maximum SPI slave ...
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Figure 7-14. SPI Master Mode with (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI Table 7-42. SPI Timing, Master Mode Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after ...
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Slave mode Figure 7-15. SPI Slave Mode with (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI Figure 7-16. SPI Slave Mode with (CPOL= NCPHA (CPOL= NCPHA= 1) SPCK MISO MOSI Figure ...
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Table 7-43. SPI Timing, Slave Mode Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup time before SPCK rises SPI8 MOSI hold time after SPCK rises SPI9 SPCK rising to MISO delay SPI10 MOSI setup time before SPCK ...
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TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more information. Table 7-44. TWI-Bus Timing Requirements Symbol Parameter t TWCK and TWD rise time r t TWCK and TWD fall time f t (Repeated) ...
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JTAG Timing Figure 7-18. JTAG Interface Signals TMS/TDI Boundary Scan Inputs Boundary Scan Outputs (1) Table 7-45. JTAG Timings Symbol Parameter JTAG0 TCK Low Half-period JTAG1 TCK High Half-period JTAG2 TCK Period JTAG3 TDI, TMS Setup before TCK High ...
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Mechanical Characteristics 8.1 Thermal Considerations 8.1.1 Thermal Data Table 8-1 Table 8-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC 8.1.2 Junction Temperature The average chip-junction temperature where: • ...
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Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. Package Characteristics Moisture Sensitivity Level Table 8-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32145AS–12/2011 AT32UC3L0128/256 mg MSL3 MS-026 E3 64 ...
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Figure 8-2. QFN-48 Package Drawing Note: Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. Package Characteristics Moisture ...
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Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32145AS–12/2011 AT32UC3L0128/256 mg MSL3 N ...
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Soldering Profile Table 8-11 Table 8-11. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Time Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature ...
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... Ordering Information Table 9-1. Ordering Information Device Ordering Code AT32UC3L0256-AUTES AT32UC3L0256-AUT AT32UC3L0256-AUR AT32UC3L0256-ZAUTES AT32UC3L0256 AT32UC3L0256-ZAUT AT32UC3L0256-ZAUR AT32UC3L0256-D3HES AT32UC3L0256-D3HT AT32UC3L0256-D3HR AT32UC3L0128-AUT AT32UC3L0128-AUR AT32UC3L0128-ZAUT AT32UC3L0128 AT32UC3L0128-ZAUR AT32UC3L0128-D3HT AT32UC3L0128-D3HR 32145AS–12/2011 Carrier Type Package Package Type ES Tray TQFP 48 Tape & Reel JESD97 Classification E3 ES ...
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Errata 10.1 Rev. C 10.1.1 SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed ...
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SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and ...
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PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquired count values. Fix/Workaround Enable ...
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The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca- tion in the SCIF memory range. Fix/Workaround None. 10.2.2 WDT 1. WDT Control Register does not have synchronization feedback When writing to the Timeout ...
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Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 6. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate ...
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Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers ...
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Rev. A 10.3.1 Device 1. JTAGID is wrong The JTAGID is 0x021DF03F. Fix/Workaround None. 10.3.2 FLASHCDW 1. General-purpose fuse programming does not work The general-purpose fuses cannot be programmed and are stuck at 1. Please refer to the Fuse ...
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If the CPU is in idle or frozen sleep mode and a module state that triggers sleep walk- ing, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock ...
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None. 10.3.5 WDT 1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi- ately ...
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SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control ...
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When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for the same duration receiving data. When TWIS releases TWCK, it releases TWD at the same time. This can ...
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Autonomous CAT acquisition must be longer than AST source clock period When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the CAT bus clock is turned off, the CAT will start several acquisitions if ...
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Enable pull-ups on PB13 to PB27 by writing 0x0FFFE000 to the PUERS1 register in the GPIO. 3. PA17 has low ESD tolerance PA17 only tolerates 500V ESD pulses (Human Body Model). Fix/Workaround Care must be taken during manufacturing and PCB ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. A – 05/2010 1. 32145AS–12/2011 Initial revision. ...
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Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 Package and Pinout ................................................................................. 7 4 Memories ................................................................................................ 18 5 Supply and Startup Considerations ..................................................... 22 6 Programming and Debugging .............................................................. 27 7 Electrical Characteristics ...
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Mechanical Characteristics ................................................................... 63 9 Ordering Information ............................................................................. 68 10 Errata ....................................................................................................... 69 11 Datasheet Revision History .................................................................. 82 Table of Contents....................................................................................... i 32145AS–12/2011 8.1 Thermal Considerations ..................................................................................63 8.2 Package Drawings ...........................................................................................64 8.3 Soldering Profile ..............................................................................................67 10.1 Rev. C ...
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