AT83C5134 Atmel Corporation, AT83C5134 Datasheet
AT83C5134
Specifications of AT83C5134
Related parts for AT83C5134
AT83C5134 Summary of contents
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... Packages: Die SO28, QFN32, MLF48, TQFP64 Notes: 1. EEPROM only available on MLF48 1. Description AT83C5134/35/36 are high performance ROM versions of the 80C51 single-chip 8-bit microcontrollers with full speed USB functions. AT83C5134/35 is pin compatible with AT89C5130A 16- Kbytes In-System Programmable Flash microcontrollers. 8-bit Microcontroller with Full Speed USB Device AT83C5134 ...
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... Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator. In addition, AT83C5134/35/36 has an on-chip expanded RAM of 1024 bytes (ERAM), a dual- data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA pro- grammable LED current sources, a programmable hardware watchdog and a power-on reset ...
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... ERAM 32Kx8 ROM 1Kx8 RAM + 256x8 BRG C51 CORE Parallel I/O Ports & Ext. Bus INT Ctrl Port 0Port 1 Port 2 Port 3 (2) (2) AT83C5134/35/36 (1) (1) (1) (1) (1) (1) (1) EEPROM* 1Kx8 PCA SPI TWI Timer2 TWI interface Key Watch USB Board Dog Port 4 ...
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... Pinout Description 4.1 Pinout Figure 4-1. AT83C5134/35/36 4 AT83C5134/35/36 64-pin VQFP Pinout P2.3/A11 3 P2.4/A12 4 P2.5/A13 5 XTAL2 6 XTAL1 7 P2.6/A14 8 P2.7/A15 VQFP64 9 VDD 10 AVDD AVSS P3.0/RxD ...
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... Figure 4-2. Figure 4-3. 7683C–USB–11/07 AT83C5134/35/36 48-pin MLF Pinout P4.1/SDA 1 P2.3/A11 2 P2.4/A12 3 4 P2.5/A13 5 XTAL2 6 XTAL1 P2.6/A14 7 MLF48 P2.7/A15 8 9 VDD AVDD 10 AVSS 11 P3.0/RxD AT83C5134/35/36 28-pin SO Pinout P1.5/CEX2/KIN5/MISO 1 P1.6/CEX3/KIN6/SCK 2 P1.7/CEX4/KIN7/MOSI 3 P4.0/SCL 4 SO28 P4 ...
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... Figure 4-4. 4.2 Signals All the AT83C5134/35/36 signals are detailed by functionality on Table 4-1 through Table 4-12. Table 4-1. Signal Name KIN[7:0) Table 4-2. Signal Name ECI CEX[4:0] AT83C5134/35/36 6 AT83C5134/35/36 32-pin QFN Pinout P4.1/SDA 1 XTAL2 2 XTAL1 3 VDD 4 AVDD 5 AVSS 6 P3.0/RxD 7 PLLF ...
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... Direct Drive LED Output These pins can be directly connected to the Cathode of standard LEDs without O external current limiting resistors. The typical current of each output can be programmed by software mA. Several outputs can be connected together to get higher drive capabilities. AT83C5134/35/36 Alternate Function P3.0 P3.1 Alternate Function P3 ...
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... Name SS MISO SCK MOSI Table 4-8. Signal Name P0[7:0] P1[7:0] P2[7:0] AT83C5134/35/36 8 TWI Signal Description Type Description SCL: TWI Serial Clock I/O SCL output the serial clock to slave peripherals. SCL input the serial clock from master. SDA: TWI Serial Data I/O SCL is the bidirectional TWI data line. ...
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... Multiplexed Address/Data LSB for external access I/O Data LSB for Slave port access (used for 8-bit and 16-bit modes) Address Bus MSB for external access I/O Data MSB for Slave port access (used for 16-bit mode only) AT83C5134/35/36 Alternate Function LED[3:0] RxD TxD INT0 ...
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... EA Table 4-12. Signal Name AVSS AVDD VSS VDD VREF AT83C5134/35/36 10 Type Description Read Signal Read signal asserted during external data memory read operation. I/O Control input for slave port read access cycles. Write Signal Write signal asserted during external data memory write operation. ...
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... The following figure represents the typical wiring schematic. Figure 5-1. Typical Application USB VBUS D+ D- GND VSS 150pF 7683C–USB–11/07 VDD 100nF 4.7µF VSS VSS 1.5K VRef AT83C5134/35/3 27R D+ 27R D- PLLF 560 820pF VSS VSS VSS AT83C5134/35/36 100nF VSS XTAL1 22pF Q 22pF XTAL2 VSS 11 ...
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... PCB Recommandations Figure 5-2. Note: Figure 5-3. AT83C5134/35/36 12 USB Pads Components must be close to the microcontroller VRef possible, isolate D+ and D- signals from other signals with ground wires No sharp angle in above drawing. USB PLL Components must be close to the microcontroller Isolate filter components with a ground wire ...
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... Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller. The AT83C5134/35/36 X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 6-1) that can be configured with off-chip components as a Pierce oscillator (see Figure 6-2). Value of capacitors and crystal characteristics are detailed in the section “ ...
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... PLL 6.3.1 PLL Description The AT83C5134/35/36 PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 6-3 shows the internal structure of the PLL. The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the ...
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... Configure Dividers N3:0 = xxxxb R3:0 = xxxxb Enable PLL PLLEN = 1 PLL Locked? LOCK = 1? Typical Divider Values R+1 3 MHz 16 6 MHz 8 8 MHz 6 12 MHz 4 16 MHz 3 18 MHz 8 20 MHz 12 24 MHz 2 AT83C5134/35/ VSS VSS Table 6-1. N+1 PLLDIV 1 F0h 1 70h 1 50h 1 30h 1 20h 3 72h 5 B4h 1 ...
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... Oscillator Frequency 6.4 Registers Table 6-2. 7 TWIX2 Bit Number Reset Value = 0000 0000b AT83C5134/35/36 16 R+1 32 MHz 3 40 MHz 12 CKCON0 (S:8Fh) Clock Control Register WDX2 PCAX2 SIX2 Bit Mnemonic Description TWI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit TWIX2 has no effect ...
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... Clear to disable the PLL. PLL Lock Indicator PLOCK Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked. PLLDIV (S:A4h) PLL Divider Register Bit Mnemonic Description R3:0 PLL R Divider Bits N3:0 PLL N Divider Bits AT83C5134/35/ EXT48 PLLEN ...
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... SFR Mapping The Special Function Registers (SFRs) of the AT83C5134/35/36 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
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... SSCON SSCS 0000 0000 1111 1000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C AT83C5134/35/36 5/D 6/E 7/F CCAP3H CCAP4H XXXX XXXX XXXX XXXX CCAP3L CCAP4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 X000 0000 UEPRST ...
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... CCh Timer/Counter 2 Low byte Timer/Counter 0 and 1 TCON 88h control Timer/Counter 0 and 1 TMOD 89h Modes T2CON C8h Timer/Counter 2 control T2MOD C9h Timer/Counter 2 Mode AT83C5134/35/36 20 C51 Core SFRs Add Name 7 6 E0h Accumulator F0h B Register Program Status D0h Word Stack Pointer 81h LSB of SPX ...
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... BRR CCF4 CIDL WDTE ECOM0 CAPP0 CAPN0 ECOM1 CAPP1 CAPN1 ECOM2 CAPP2 CAPN2 ECOM3 CAPP3 CAPN3 ECOM4 CAPP4 CAPN4 AT83C5134/35/ TB8 RB8 TBCK RBCK SPD SRC CCF3 ...
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... A3h PLL Control PLLDIV A4h PLL Divider Table 7-10. Keyboard SFRs Mnemonic Add Name Keyboard Flag KBF 9Eh Register Keyboard Input Enable KBE 9Dh Register AT83C5134/35/ CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP3H7 CCAP3H6 ...
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... EORINT EWUPCP - - EEORINT EPEN - - - DIR RXOUTB1 STALLRQ TXRDY - - EP5RST EP4RST - - EP5INT EP4INT - - EP5INTE EP4INTE FDAT7 FDAT6 FDAT5 FDAT4 AT83C5134/35/ KBLS4 KBLS3 KBLS2 KBLS1 STO SI AA CR1 SC1 SC0 - - SD4 SD3 SD2 SD1 MSTR ...
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... Other SFR’s Mnemonic Add Name PCON 87h Power Control AUXR 8Eh Auxiliary Register 0 AUXR1 A2h Auxiliary Register 1 CKCON0 8Fh Clock Control 0 CKCON1 AFh Clock Control 1 LEDCON F1h LED Control AT83C5134/35/ BYCT7 BYCT6 BYCT5 BYCT4 - - - - FNUM7 FNUM6 FNUM5 FNUM4 - - CRCOK CRCERR ...
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... Program/Code Memory The AT83C5134/35/36 implement Kbytes of on-chip program/code memory. Figure 8-1 shows the split of internal and external program/code memory spaces depending on the product. Figure 8-1. Note: 8.1 External Code Memory Access 8.1.1 Memory Interface The external memory interface comprises the external bus (Port 0 and Port 2) as well as the bus control signals (PSEN, and ALE) ...
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... PSEN 8.1.2 External Bus Cycles This section describes the bus cycles the AT83C5134/35/36 executes to fetch code (see Figure 8-3) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri- ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode (see the clock Section) ...
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... The oscillator is configured to run from MHz 1 0 The oscillator is configured to run from MHz 0 1 The oscillator is configured to run from MHz 0 0 This configuration shouldn’t be set - Reserved - Reserved User Program Lock Bits LB1-0 See Table 9-2 on page 28 AT83C5134/35/ LB1 0 LB0 27 ...
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... Program ROM lock Bits The lock bits when programmed according to Table 9-2 will provide different level of protection for the on-chip code and data. Table 9-2. Program Lock Bits Security level unprogrammed P: programmed AT83C5134/35/36 28 Program Lock bits Protection Description LB1 LB0 program lock feature enabled Reading ROM data from programmer is disabled. 7683C– ...
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... In order to access this memory necessary to use software subroutines according to the AT 24Cx x da tashee t. Never thele ss , beca use the in te rnal pul l sis tors of the AT83C5134/35/36 is quite high (around 100KΩ), the protocol should be slowed in order to be sure that the SDA pin can rise to the high level before reading it. ...
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... Table 11-1. Table 11-1. Part Number AT83C5134/35/36 The AT83C5134/35/36 has on-chip data memory which is mapped into the following four sepa- rate segments. 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only. ...
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... The value read from this bit is indeterminate. Do not set this bit Pulse length Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods M0 (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. AT83C5134/35/ XRS1 XRS0 ...
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... Bit Number Reset Value = 0X0X 1100b Not bit addressable AT83C5134/35/36 32 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit XRS1 ERAM Size XRS1XRS0 ERAM size 0 0 256 bytes 0 1 512 bytes XRS0 1 0 768 bytes ...
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... Timer 2 The Timer 2 in the AT83C5134/35/36 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2 controlled by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. ...
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... Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. • Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. • To start the timer, set TR2 run control bit in T2CON register. AT83C5134/35/ ...
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... RCAP2H and RCAP2L registers. Figure 12-2. Clock-out Mode C/ 7683C–USB–11/ CLK PERIPH T2 T2EX AT83C5134/35/36 TR2 T2CON TH2 TL2 (8-bit) (8-bit) RCAP2H RCAP2L ...
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... Table 12-1. 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT83C5134/35/36 36 T2CON Register T2CON - Timer 2 Control Register (C8h EXF2 RCLK TCLK Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. ...
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... The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. AT83C5134/35/ T2OE 0 DCEN ...
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... The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can be programmed to run at: • 1/6 the • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) AT83C5134/35/36 38 ÷ ) CLK PERIPH ÷ ) ...
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... CPS0 1 0 Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = f PCA Enable Counter Overflow Interrupt ECF Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt. AT83C5134/35/36 To PCA modules overflow Bit Up Counter CMOD ECF 0xD9 CCON 0xD8 ...
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... These flags can only be cleared by software. Table 13- Bit Number AT83C5134/35/36 40 CCON Register CCON - PCA Counter Control Register (D8h – CCF4 Bit Mnemonic Description PCA Counter Overflow flag CF Set by hardware when the counter rolls over ...
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... PCA Module 1 Interrupt Flag CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 Interrupt Flag CCF0 Must be cleared by software. Set by hardware when a match or capture occurs CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 AT83C5134/35/36 CCON 0xD8 To Interrupt priority decoder IE.6 IE ...
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... CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh Bit Number AT83C5134/35/36 42 CCAPMn Registers ( ECOMn CAPPn CAPNn Bit Mnemonic Description Reserved - The value read from this bit is indeterminate ...
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... AT83C5134/35/36 PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger CEXn 16-bit capture by a transition CEXn 16-bit Software Timer/Compare ...
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... Bit Number Reset Value = XXXX XXXXb Not bit addressable Table 13- PCA Counter Register High (0F9h Bit Number Reset Value = 0000 0000b Not bit addressable AT83C5134/35/36 44 CCAPnH Registers ( Bit Mnemonic Description PCA Module n Compare/Capture Control - CCAPnH Value CCAPnL Registers (n = 0-4) ...
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... SFR) bits for the module are both set (see Figure 13-4). 7683C–USB–11/07 CL Register Bit Mnemonic Description PCA Counter - CL Value CR CCF4 CCF3 CCF2 CCF1 CCF0 Capture CAPPn CAPNn MATn TOGn PWMn ECCFn AT83C5134/35/ CCON 0xD8 PCA Counter/Timer CH CL CCAPnH CCAPnL CCAPMn 0xDA to 0xDE 1 0 ...
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... PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see Figure 13-5). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. AT83C5134/35/ ...
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... The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. 7683C–USB–11/ CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16-bit Comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn AT83C5134/35/36 CCON 0xD8 PCA IT CEXn CCAPMn 0xDA to 0xDE 47 ...
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... Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. AT83C5134/35/36 48 CCAPnH ...
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... Serial I/O Port The serial I/O port in the AT83C5134/35/36 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates ...
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... To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b Slave B:SADDR1111 0011b AT83C5134/35/36 50 RXD ...
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... XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. 7683C–USB–11/07 SADEN1111 1101b Given1111 00X1b SADDR0101 0110b SADEN1111 1100b SADEN1111 1010b Broadcast1111 1X11b, SADEN1111 1001b Broadcast1111 1X11B, SADEN1111 1101b Broadcast1111 1111b AT83C5134/35/36 51 ...
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... Reset Value = 0000 0000b Not bit addressable 14.3 Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 14-4. Baud Rate Selection AT83C5134/35/ ...
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... SMOD1 2 (BRL) = 256 - (1-SPD Baud_Rate SCON Register – SCON Serial Control Register (98h SM1 SM2 REN AT83C5134/35/36 Clock Source Clock Source UART Tx UART Rx Timer 1 Timer 2 Timer 1 Timer 2 INT_BRG INT_BRG Timer 1 INT_BRG Timer 2 INT_BRG INT_BRG ...
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... Reset Value = 0000 0000b Bit addressable AT83C5134/35/36 54 Bit Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. FE Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection ...
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... F = 16.384 MHz OSC BRL 4800 247 2400 238 1200 220 600 185 6 5 – – – – – – AT83C5134/35/36 F OSC Error (%) BRL 1.23 243 1.23 230 1.23 217 1.23 204 0.63 178 0.31 100 1. OSC Error (%) BRL 1.23 243 1.23 230 1.23 202 ...
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... Reset Value = 0000 0000b Table 14-2. T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT83C5134/35/ – – – T2CON Register EXF2 RCLK TCLK Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software ...
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... Set by user for general-purpose usage. Power-down Mode Bit PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode Bit IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. AT83C5134/35/ GF1 GF0 PD rises from 0 to its nominal voltage. Can also be set by 0 ...
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... Table 14-4. BDRCON - Baud Rate Control Register (9Bh Bit Number Reset Value = xxx0 0000b Not bit addressable AT83C5134/35/36 58 BDRCON Register BRR Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit Reserved - The value read from this bit is indeterminate ...
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... The value read from this bit is indeterminate. Do not set this bit. GF3 This bit is a general-purpose user flag. 0 Always cleared. Reserved - The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection DPS Cleared to select DPTR0. Set to select DPTR1. AT83C5134/35/36 External Data Memory GF3 DPS 59 ...
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... In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc- tion (INC AUXR1), the routine will exit with DPS in the opposite state. AT83C5134/35/36 60 AUXR1 EQU 0A2H ...
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... Interrupt System 16.1 Overview The AT83C5134/35/36 has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1. ...
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... If interrupt requests of the same priority level are received simul- taneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. AT83C5134/35/36 62 (Table 16-4). Table 16-1. shows the bit values and priority levels associated with Priority Level Bit Values IPH ...
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... Cleared to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. AT83C5134/35/ ET1 EX1 ET0 0 EX0 63 ...
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... IPL0 - Interrupt Priority Register (B8h Bit Number Reset Value = x000 0000b Bit addressable AT83C5134/35/36 64 IPL0 Register PPCL PT2L PSL Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit PPCL Refer to PPCH for priority level ...
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... Highest Timer 0 overflow interrupt Priority High bit PT0H PT0L Priority Level 0 0 Lowest PT0H Highest External interrupt 0 Priority High bit PX0H PX0L Priority Level 0 0 Lowest PX0H Highest AT83C5134/35/ PT1H PX1H PT0H 0 PX0H 65 ...
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... Table 16-5. IEN1 - Interrupt Enable Register (B1h Bit Number Reset Value = x0xx x000b Not bit addressable AT83C5134/35/36 66 IEN1 Register EUSB - - Bit Mnemonic Description - Reserved USB Interrupt Enable bit EUSB Cleared to disable USB interrupt. Set to enable USB interrupt. ...
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... The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority bit PSPIL Refer to PSPIH for priority level. TWI Interrupt Priority bit PTWIL Refer to PTWIH for priority level. Keyboard Interrupt Priority bit PKBL Refer to PKBH for priority level. AT83C5134/35/ PSPIL PTWIL PKBDL 0 67 ...
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... IPH1 - Interrupt Priority High Register (B3h Bit Number Reset Value = X0XX X000b Not bit addressable AT83C5134/35/36 68 IPH1 Register PUSBH - - Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. USB Interrupt Priority High bit ...
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... Timer PCA 8 8 Keyboard 9 9 TWI 10 10 SPI USB 15 15 AT83C5134/35/36 Vector Interrupt Request Address 0000h IE0 0003h TF0 000Bh IE1 0013h IF1 001Bh RI+TI 0023h TF2+EXF2 002Bh CF + CCFn (n = 0-4) 0033h KBDIT 003Bh TWIIT 0043h SPIIT 004Bh ...
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... Keyboard Interface 17.1 Introduction The AT83C5134/35/36 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes. ...
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... Cleared by hardware when reading KBF SFR by software. Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a KBF0 Keyboard interrupt request if the KBIE.0 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software. AT83C5134/35/ KBF3 KBF2 ...
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... Table 17-2. KBE - Keyboard Input Enable Register (9Dh) 7 KBE7 Bit Number Reset Value = 0000 0000b AT83C5134/35/36 72 KBE Register KBE6 KBE5 KBE4 Bit Mnemonic Description Keyboard line 7 Enable bit KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. ...
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... Keyboard line 1 Level Selection bit KBLS1 Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. AT83C5134/35/ KBLS3 KBLS2 KBLS1 0 ...
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... Programmable LED AT83C5134/35/36 have programmable LED current sources, configured by the register LEDCON. Table 18-1. LEDCON (S:F1h) LED Control Register 7 Bit Number 7:6 5:4 3:2 1:0 Reset Value = 00h AT83C5134/35/36 74 LEDCON Register LED3 LED2 Bit Mnemonic Description Port LED3 Configuration 0 0 Standard C51 Port LED3 ...
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... Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. 7683C–USB–11/07 shows a typical SPI bus configuration using one Master controller and many Slave MISO MOSI SCK SS VDD Master Slave 4 AT83C5134/35/36 Slave 1 Slave 3 Slave 2 75 ...
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... AT83C5134/35/ Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this mode, the SS is used to start the transmission. gives the different clock rates selected by SPR2:SPR1:SPR0: ...
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... SPI module. FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS MSTR SPI Interrupt Request SPIF AT83C5134/35/36 Internal Bus SPDAT Shift Register Receive Data Register Pin Control Logic Clock M Logic ...
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... CPHA defines the edges on which the input data are sampled and the edges on which the out- put data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device AT83C5134/35/36 78 8-bit Shift Register MOSI SPI Clock Generator Master MCU The SPI module should be configured as a Master before it is enabled (SPEN set) ...
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... MSB bit6 bit5 bit4 bit3 Byte 1 Byte 2 Figure 19-5, the first SCK edge is the MSB capture strobe. Therefore the Slave shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driv- AT83C5134/35/ bit2 bit1 LSB bit2 bit1 LSB 6 ...
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... Flag SPIF (SP Data Transfer) MODF (Mode Fault) Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. AT83C5134/35/36 80 SPI Interrupts Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = “0”) ...
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... MSTR Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. Clock Polarity CPOL Cleared to have the SCK set to “0” in idle state. Set to have the SCK set to “1” in idle state. AT83C5134/35/36 SPI CPU Interrupt Request CPOL ...
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... SPSTA - Serial Peripheral Status and Control register (0C4H) 7 SPIF Bit Number AT83C5134/35/36 82 Bit Mnemonic Description Clock Phase CPHA Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). ...
Page 83
... The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. (Table 19- read/write buffer for the receive data regis- SPDAT Register AT83C5134/35/ ...
Page 84
... ICs connected to them. The serial data transfer is limited to 100 Kbit/s in standard mode. Various communication configuration can be designed using this bus. 20-1 shows a typical 2-wire bus configuration. All the devices connected to the bus can be mas- ter and slave. Figure 20-1. 2-wire Bus Configuration SCL SDA AT83C5134/35/ TWI ... device1 device2 device3 ...
Page 85
... Stage 7683C–USB–11/07 Address Register SSADR Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status Status Decoder Bits Status Register SSCS AT83C5134/35/36 8 ACK CLK PERIPH Interrupt ...
Page 86
... Slave receiver Data transfer in each mode of operation is shown in Table to Table 20-9 and Figure 20-4. to Figure 20-7.. These figures contain the following abbreviations START condition AT83C5134/35/36 86 Table 20-11), the Synchronous Serial Control and Status register (SSCS; shows how a data transfer is accomplished on the 2-wire bus. MSB ...
Page 87
... The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave 7683C–USB–11/07 SSCON Initialization SSIE STA STO AT83C5134/35/ CR1 CR0 0 X bit rate bit rate 87 ...
Page 88
... While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the module from the 2-wire bus. AT83C5134/35/36 88 SSADR: Slave Receiver Mode Initialization A5 ...
Page 89
... SDA and SLC must be set to logic 1. Table 20-4. CR2 CR1 CR0 7683C–USB–11/07 Bit Frequency Configuration Bit Frequency ( kHz MHz MHz OSCA OSCA 47 62.5 53.5 71.5 62 100 AT83C5134/35/36 F divided by OSCA 256 224 192 160 89 ...
Page 90
... Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave From master to slave AT83C5134/35/36 90 From slave to master Bit Frequency ( kHz MHz MHz OSCA OSCA - - 100 133 ...
Page 91
... AT83C5134/35/36 Next Action Taken by Two-wire Hardware X SLA+W will be transmitted. SLA+W will be transmitted. X SLA+R will be transmitted. X Logic will switch to master receiver mode Data byte will be transmitted. X Repeated START will be transmitted. X STOP condition will be transmitted and SSSTO flag X will be reset ...
Page 92
... Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or acknowledge bit Arbitration lost and addressed as slave From master to slave From slave to master AT83C5134/35/ Data Data 50h 40h A P 48h Other master ...
Page 93
... AT83C5134/35/36 Next Action Taken by Two-wire Hardware X SLA+R will be transmitted. SLA+R will be transmitted. X SLA+W will be transmitted. X Logic will switch to master transmitter mode. Two-wire bus will be released and not addressed X slave mode will be entered. A START condition will be transmitted when the bus X becomes free ...
Page 94
... Reception of the general call address and one or more data bytes. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave by general call From master to slave From slave to master AT83C5134/35/ SLA W A 60h A 68h General Call ...
Page 95
... Read data byte or Read data byte AT83C5134/35/36 AA Next Action Taken By 2-wire Software Data byte will be received and NOT ACK will be 0 returned Data byte will be received and ACK will be 1 returned Data byte will be received and NOT ACK will be ...
Page 96
... Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START condition has been A0h received while still addressed as slave AT83C5134/35/36 96 Application Software Response To/from SSDAT To SSCON STA STO SI Read data byte ...
Page 97
... Load data byte X 0 Load data byte Load data byte X 0 Load data byte Load data byte X 0 AT83C5134/35/36 Data B8h C0h All 1’s A C8h SI AA Next Action Taken By 2-wire Software Last data byte will be transmitted and NOT ACK 0 ...
Page 98
... Table 20-9. Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware No relevant state information F8h available; SI= 0 Bus error due to an illegal 00h START or STOP condition AT83C5134/35/36 98 Application Software Response To/from SSDAT To SSCON STA STO SI No SSDAT action SSDAT action or ...
Page 99
... Address bit 7 or Data bit 7. SD6 Address bit 6 or Data bit 6. SD5 Address bit 5 or Data bit 5. SD4 Address bit 4 or Data bit 4. SD3 Address bit 3 or Data bit 3. SD2 Address bit 2 or Data bit 2. AT83C5134/35/ CR1 SD3 SD2 SD1 3 ...
Page 100
... Table 20-13. SSADR (096h) - Synchronous Serial Address Register (read/write Bit Number AT83C5134/35/36 100 Bit Mnemonic Description SD1 Address bit 1 or Data bit 1. SD0 Address bit 0 (R/W) or Data bit SC3 SC2 SC1 Bit Mnemonic ...
Page 101
... The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and un-stuffing. • CRC generation and checking. • Handshakes. • TOKEN type identifying. 7683C–USB–11/07 48 MHz +/- 0.25% DPLL 12 MHz SIE AT83C5134/35/36 C51 Microcontroller Interface UFI MHz UC_sysclk 101 ...
Page 102
... Function Interface Unit (FIU) The Function Interface Unit provides the interface between the AT89C5131 and the SIE. It man- ages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. AT83C5134/35/36 102 NRZI ‘NRZ Bit Un-stuffing ...
Page 103
... Endpoint 2 Endpoint 1 DPR Control Endpoint 0 USB Side User DPRAM OUT DATA1 ACK interrupt C51 Endpoint FIFO read (n bytes) IN DATA1 (See “Clock Controller” on page AT83C5134/35/36 C51 CSREG Microcontroller Interface Registers Bank DPR Control MHz mP side UC_sysclk OUT DATA1 NACK ...
Page 104
... All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The configuration of an endpoint is performed by setting the field EPTYPE with the following values: – Control:EPTYPE = 00b – Isochronous:EPTYPE = 01b – Bulk:EPTYPE = 10b – Interrupt:EPTYPE = 11b AT83C5134/35/36 104 UEPCON0 UEPDAT0 0 UBYCTL0 1 2 ...
Page 105
... FIFO Mapping Depending on the selected endpoint through the UEPNUM register, the UEPDATX register allows to access the corresponding endpoint data fifo. 7683C–USB–11/07 Summary of Endpoint Configuration EPEN AT83C5134/35/36 EPDIR EPTYPE UEPCONX Xb XXb 0XXX XXXb Xb 00b 80h 1b 10b 86h 0b ...
Page 106
... Warning 1: The byte counter is not updated. Warning 2: Do not write more bytes than supported by the corresponding endpoint. 21.4 Bulk/Interrupt Transactions Bulk and Interrupt transactions are managed in the same way. AT83C5134/35/36 106 UEPCON0 UEPDAT0 UBYCTH0 UBYCTL0 UEPCON5 ...
Page 107
... HOST UFI OUT DATA0 (n bytes) ACK RXOUTB0 OUT DATA1 NAK OUT DATA1 NAK DATA1 OUT ACK RXOUTB0 AT83C5134/35/36 C51 Endpoint FIFO read byte 1 Endpoint FIFO read byte 2 Endpoint FIFO read byte n Clear RXOUTB0 Endpoint FIFO read byte 1 107 ...
Page 108
... The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new valid packet receipt. The firmware has to clear one of these two bits after having read all the data FIFO to allow a new valid packet to be stored in the corresponding bank. AT83C5134/35/36 108 HOST UFI ...
Page 109
... All USB retry mechanisms are automatically managed by the USB controller. 7683C–USB–11/07 UFI HOST IN NAK IN DATA0 (n Bytes) ACK TXCMPL AT83C5134/35/36 C51 Endpoint FIFO Write Byte 1 Endpoint FIFO Write Byte 2 Endpoint FIFO Write Byte n Set TXRDY Clear TXCMPL Endpoint FIFO Write Byte 1 109 ...
Page 110
... Note that in the example above, the firmware clears the Transmit Complete bit (TXCMPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1. AT83C5134/35/36 110 HOST ...
Page 111
... To send a STALL handshake, see • For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 7683C–USB–11/07 AT83C5134/35/36 “STALL Handshake” on page 114. “Bulk/Interrupt IN Transactions in Standard Mode” on page “ ...
Page 112
... FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firm- ware, the data sent by the Host on the bank 1 endpoint FIFO will be lost. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new packet receipt. AT83C5134/35/36 112 7683C–USB–11/07 ...
Page 113
... The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still enabled, but all the USB registers are reset by hardware. The firmware will clear the EORINT bit to allow the next USB reset detection. 7683C–USB–11/07 AT83C5134/35/36 113 ...
Page 114
... The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSP- CLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake- up event is detected. AT83C5134/35/36 114 7683C–USB–11/07 ...
Page 115
... USB controller from its Suspend mode. The USB controller is then re-activated. Figure 21-11. Example of a Suspend/Resume Management 7683C–USB–11/07 Detection of a SUSPEND State WUPCPU Detection of a RESUME State AT83C5134/35/36 USB Controller Init SPINT Clear SPINT Set SUSPCLK Disable PLL microcontroller in Power-down ...
Page 116
... When the upstream resume is completed, the UPRSM bit is reset hardware. The firmware will then clear the SDRMWUP bit. Figure 21-12. Example of REMOTE WAKEUP Management SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND State Upstream RESUME Sent AT83C5134/35/36 116 USB Controller Init Set RMWUPE SPINT Suspend Management ...
Page 117
... Detach Simulation In order to be re-enumerated by the Host, the AT83C5134/35/36 has the possibility to simulate a DETACH - ATTACH of the USB bus. The V REF up as shown in set the USBCON register. Maintaining this output in high impedance for more than 3 µs will simulate the disconnection of the device. When resetting the DETACH bit, an attach is then simulated ...
Page 118
... Interrupt Enable Register” on page Frame packet has been received. • WUPCPU: Wake-Up CPU Interrupt Interrupt Enable Register” on page detected on the USB bus, after a SUSPEND state. • SPINT: Suspend Interrupt Enable Register” on page on the USB bus. AT83C5134/35/36 118 Priority Levels IPHUSB IPLUSB ...
Page 119
... Figure 21-16. USB Interrupt Control Block Diagram Endpoint 0..5) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 7683C–USB–11/07 EPXINT UEPINT.X EPXIE UEPIEN.X AT83C5134/35/36 EUSB IE1.6 119 ...
Page 120
... USB Registers Table 21-3. 7 USBE Bit Number Reset Value = 00h AT83C5134/35/36 120 USBCON Register USBCON (S:BCh) USB Global Control Register SUSPCLK SDRMWUP DETACH Bit Mnemonic Description USB Enable Set this bit to enable the USB controller. USBE Clear this bit to disable and reset the USB controller, to disable the USB transceiver an to disable the USB controller clock inputs ...
Page 121
... This bit is set by hardware when a USB Suspend (Idle bus for three frame periods state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in see SPINT Table 21-5 on page 122. This bit will be cleared by software BEFORE any other USB operation to re-activate the macro. AT83C5134/35/ SOFINT - - Table 21-5 on page 122 ...
Page 122
... Table 21- Bit Number 7 Reset Value = 10h AT83C5134/35/36 122 USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register EWUPCPU EEORINT Bit Mnemonic Description Reserved - The value read from these bits is always 0. Do not set these bits. Enable Wake Up CPU Interrupt Set this bit to enable Wake Up CPU Interrupt ...
Page 123
... EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number), UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) or UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register. This value can AT83C5134/35/ UADD3 ...
Page 124
... EPEN Bit Number 1-0 Note: Reset Value = 80h when UEPNUM = 0 (default Control Endpoint) Reset Value = 00h otherwise for all other endpoints AT83C5134/35/36 124 UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register Bit Mnemonic Description Endpoint Enable Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will ...
Page 125
... OUT packets to the endpoint bank 1 are rejected (NAK’ed) (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on AT83C5134/35/ ...
Page 126
... UBYCTHX (S:E3h) USB Byte Count High Register Bit Number Bit Mnemonic 7-2 - 2-0 BYCT[10:8] Reset Value = 00h AT83C5134/35/36 126 (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number FDAT5 FDAT4 FDAT3 (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number ...
Page 127
... Endpoint 0 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset EP0RST or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. AT83C5134/35/ EP3RST ...
Page 128
... Table 21-14. UEPINT Register 7 - Bit Number Reset Value = 00h AT83C5134/35/36 128 UEPINT (S:F8h read-only) USB Endpoint Interrupt Register EP5INT EP4INT Bit Mnemonic Description Reserved - The value read from this bit is always 0. Do not set this bit. Reserved - The value read from this bit is always 0 ...
Page 129
... Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 0 Interrupt Enable EP0INTE Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. AT83C5134/35/ EP3INTE EP2INTE ...
Page 130
... Number 2-0 Reset Value = 00h Table 21-17. UFNUML Register 7 FNUM7 Bit Number Reset Value = 00h AT83C5134/35/36 130 UFNUMH (S:BBh, read-only) USB Frame Number High Register CRCOK CRCERR Bit Mnemonic Description Frame Number CRC OK This bit is set by hardware when a new Frame Number in Start of Frame Packet is CRCOK received without CRC error ...
Page 131
... The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-up resistor allowing power-on reset by simply connect- ing an external capacitor to V characteristics are discussed in the Section “DC Characteristics” of the AT83C5134/35/36 datasheet. Figure 22-2. Reset Circuitry and Power-On Reset 22 ...
Page 132
... Figure 22-3. Recommended Reset Output Schematic AT83C5134/35/36 132 VDD RST RST AT89C5131A-M 1K VSS + VSS To other on-board circuitry 7683C–USB–11/07 ...
Page 133
... Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail Detect threshold level, the Reset will be applied immediately. AT83C5134/35/36 CPU core Regulated ...
Page 134
... The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted. . AT83C5134/35/36 134 t 7683C–USB–11/07 ...
Page 135
... In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT83C5134/35/36 into power-down mode. 7683C–USB–11/07 AT83C5134/35/36 can be lowered to save further power ...
Page 136
... Mode Idle Idle Power-down Power-down Note: AT83C5134/35/36 136 Power-down Phase Oscillator restart Phase If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. ...
Page 137
... Cleared by software for general-purpose usage. Power-down mode bit PD Set this bit to enter in power-down mode. Cleared by hardware when reset occurs. Idle mode bit IDL Set this bit to enter in Idle mode. Cleared by hardware when interrupt or reset occurs. AT83C5134/35/ GF1 GF0 PD 0 IDL ...
Page 138
... Table 25-2. Table 25- Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT83C5134/35/36 138 = 1 make the best use of the WDT, it should be serviced in those sec- CLK PERIPH 7 counter has been added to extend the Time-out capability MHz ...
Page 139
... WDT just before entering power-down. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT83C5134/35/36 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...
Page 140
... Cleared to access internal ERAM using MOVX DPTR. EXTRAM Set to access external memory. ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used) (default). Set , ALE is active only during a MOVX or MOVC instruction is used. AT83C5134/35/ XRS1 XRS0 EXTRAM 0 ...
Page 141
... Logical 0 Input Current ports and Input Leakage Current LI Logical Transition Current, ports and 4 C Capacitance of I/O Buffer IO I Power-down Current PD Power Supply Current Power Fail High Level Threshold PFDP AT83C5134/35/36 142 Note 2.7 - 3.6V MHz Min Typ -0.5 0 0 ( 0.7 ...
Page 142
... Pins are not guaranteed to sink current greater OL Test Condition, Active Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS AT83C5134/35/36 (5) Typ Max Unit Test Conditions (see Figure 27-4.), V CLCH CHCL , ns CLCH CHCL IL , PORT XTAL2 NC.; RST = V ...
Page 143
... Figure 27-2. I Figure 27-3. I Figure 27-4. Clock Signal Waveform for I 27.2.1 LED’s Table 27-1. LED Outputs DC Parameters Symbol Parameter I Output Low Current, P3.6 and P3.7 LED modes OL Note -20°C to +50° AT83C5134/35/36 144 Test Condition, Idle Mode RST EA (NC) XTAL2 ...
Page 144
... 2.7 - 3. Table 27-6 and Table 27-9 give the description of each AC symbols. Table 27-8 and Table 27-10 give for each range the AC parameter. Table 27-11 give the frequency derating formula of the AC parame- AT83C5134/35/ REF D + Rpad D - Rpad Min Typ 3.0 2.0 2.7 2.8 0 MHz. . Max Unit 3 ...
Page 145
... Example 170 ns CCIV 27.4.2 External Program Memory Characteristics Table 27-2. Table 27-3. AT83C5134/35/36 146 and 20 MHz, Standard clock. LLIV Symbol Description Symbol Parameter T Oscillator Clock Period T ALE Pulse Width LHLL T Address Valid to ALE AVLL T Address Hold after ALE LLAX ...
Page 146
... T CLCL T T LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T TPLAZ AVLL PXIX A0-A7 INSTR IN T AVIV ADDRESS A8-A15 AT83C5134/35/36 Standard Clock X2 Clock X Parameter ...
Page 147
... External Data Memory Characteristics Table 27-5. Table 27-6. AT83C5134/35/36 148 Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ALE to Valid Data In LLDV T Address to Valid Data In AVDV T ALE ...
Page 148
... Min QVWH T Min WHQX T Max RLAZ T Min WHLH T Max WHLH T LLWL T LLAX A0-A7 T AVWL ADDRESS OR SFR-P2 AT83C5134/35/36 X2 Clock X Parameter ...
Page 149
... External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 27.4.7 Serial Port Timing - Shift Register Mode Table 27-8. Table 27-9. Table 27-10. AC Parameters for a Variable Clock AT83C5134/35/36 150 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Symbol Description ( MHz) Symbol ...
Page 150
... Cyclic ratio in X2 mode CHCX CLCX V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC INPUT/OUTPUT 0.45V CC min for a logic “1” and 0 0 AT83C5134/35/ SET TI VALID VALID VALID VALID SET RI Min CHCX T T CLCX CLCH T CLCL 0 ...
Page 151
... This propagation delay is dependent on variables such as temperature and pin loading. Propa- gation also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT83C5134/35/36 152 STATE5 STATE6 ...
Page 152
... DJ1 Transaction Source Jitter Total for Paired t DJ2 Transactions Receiver Jitter to Next t JR1 Transaction Receiver Jitter for Paired t JR2 Transactions Signals C Clock I Data In O Data Out AT83C5134/35/36 Min Typ 50 50 Fall Time V 10 Min Typ Max Unit ...
Page 153
... T OHOL T CHCH T CHCX T CLCX T IVCL T CLIX T CLOV, T CLOX Note: AT83C5134/35/36 154 = -40 to +85°C A Symbol Parameter Clock Period Clock High Time Clock Low Time , T SS Low to Clock edge SLCL , T Input Data Valid to Clock Edge IVCH , T Input Data Hold after Clock Edge CHIX ...
Page 154
... CHCH T T CHCX CLCX T SLOV (1) SLAVE MSB OUT T T IVCH CHIX T T IVCL CLIX MSB IN 1. Not Defined but generally the LSB of the character which has just been received. AT83C5134/35/36 T CLSH T CHSH T CLCH T CHCL T T CLOX CLOV T T CHOX CHOV (1) BIT 6 ...
Page 155
... MISO (output) Note: Figure 27-8. SPI Master Waveforms (SSCPHA (output) SCK (CPOL= 0) (output) SCK (CPOL= 1) (output) MOSI (input) MISO (output) handled by software using general purpose port pin. SS AT83C5134/35/36 156 T CHCH T T CHCX CLCX T T IVCH CHIX T T IVCL CLIX MSB IN BIT 6 ...
Page 156
... EEPROM 2.7 to 3.6V EEPROM AT83C5134/35/36 Temperature Range Package Industrial & Green QFN32 Industrial & Green QFN32 Industrial & Green QFN32 Industrial & Green QFN/MLF48 Industrial & Green SO28 Industrial & Green VQFP64 Industrial & Green Die Industrial & ...
Page 157
... Packaging Information 29.1 64-lead VQFP AT83C5134/35/36 158 7683C–USB–11/07 ...
Page 158
... MLF 7683C–USB–11/07 AT83C5134/35/36 159 ...
Page 159
... AT83C5134/35/36 160 7683C–USB–11/07 ...
Page 160
... SO 7683C–USB–11/07 AT83C5134/35/36 161 ...
Page 161
... QFN32 AT83C5134/35/36 162 7683C–USB–11/07 ...
Page 162
... Document Revision History 30.1 Changes from Rev A. to Rev Added QFN32 package. 30.2 Changes from Rev B. to Rev Updated package drawings. 7683C–USB–11/07 AT83C5134/35/36 163 ...
Page 163
... Pinout Description ................................................................................... 4 5 Typical Application ................................................................................ 11 6 Clock Controller ..................................................................................... 13 7 SFR Mapping .......................................................................................... 18 8 Program/Code Memory ......................................................................... 25 9 AT89C5131 ROM .................................................................................... 27 10 Stacked EEPROM................................................................................... 29 11 On-chip Expanded RAM (ERAM) .......................................................... 30 12 Timer 2 .................................................................................................... 33 13 Programmable Counter Array (PCA).................................................... 38 AT83C5134/35/36 164 4.1 Pinout ................................................................................................................ 4 4.2 Signals............................................................................................................... 6 5.1 Recommended External components ............................................................. 11 5.2 PCB Recommandations .................................................................................. 12 6.1 Introduction...................................................................................................... 13 6.2 Oscillator.......................................................................................................... 13 6.3 PLL ...
Page 164
... Registers ......................................................................................................... 62 16.3 Interrupt Sources and Vector Addresses......................................................... 69 17.1 Introduction...................................................................................................... 70 17.2 Description....................................................................................................... 70 17.3 Registers ......................................................................................................... 71 19.1 Features .......................................................................................................... 75 19.2 Signal Description............................................................................................ 75 19.3 Functional Description ..................................................................................... 77 20.1 Description....................................................................................................... 86 20.2 Notes ............................................................................................................... 89 20.3 Registers ......................................................................................................... 99 21.1 Description..................................................................................................... 101 21.2 Configuration ................................................................................................. 103 21.3 Read/Write Data FIFO................................................................................... 105 21.4 Bulk/Interrupt Transactions............................................................................ 106 21.5 Control Transactions ..................................................................................... 111 21.6 Isochronous Transactions ............................................................................. 112 21.7 Miscellaneous................................................................................................ 113 21.8 Suspend/Resume Management .................................................................... 114 AT83C5134/35/36 165 ...
Page 165
... Reset ..................................................................................................... 131 23 Power Monitor ...................................................................................... 133 24 Power Management ............................................................................. 135 25 Hardware Watchdog Timer ................................................................. 138 26 Reduced EMI Mode .............................................................................. 141 27 Electrical Characteristics .................................................................... 142 28 Ordering Information ........................................................................... 157 29 Packaging Information ........................................................................ 158 30 Document Revision History ................................................................ 163 AT83C5134/35/36 166 21.9 Detach Simulation ......................................................................................... 117 21.10 USB Interrupt System.................................................................................... 117 21.11 USB Registers ............................................................................................... 120 22.1 Introduction ...
Page 166
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...