AT86RF231 Atmel Corporation, AT86RF231 Datasheet
AT86RF231
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AT86RF231 Summary of contents
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... Compliant to IEEE 802.15.4-2006 and IEEE 802.15.4-2003 • Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-T66, RSS-210 ™ , ™ and ISM Applications Low Power 2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE, SP100, WirelessHART, and ISM Applications AT86RF231-ZU AT86RF231-ZF 8111C–MCU Wireless–09/09 ...
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... Pin-out Diagram Figure 1-1. Note: 8111C–MCU Wireless–09/09 AT86RF231 Pin-out Diagram T86 The exposed paddle is electrically connected to the die inside the package. It shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability ...
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... Pin Descriptions Table 1-1. Pin Description AT86RF231 Pins Name Type 1 DIG3 Digital output (Ground) 2 DIG4 Digital output (Ground) 3 AVSS Ground 4 RFP RF I/O 5 RFN RF I/O 6 AVSS Ground 7 DVSS Ground 8 /RST Digital input 9 DIG1 Digital output (Ground) 10 DIG2 Digital output (Ground) 11 SLP_TR Digital input ...
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... Table 1-1. Pin Description AT86RF231 (Continued) Pins Name Type 29 AVDD Supply 30 AVSS Ground 31 AVSS Ground 32 AVSS Ground Paddle AVSS Ground 8111C–MCU Wireless–09/09 Description Regulated 1.8V voltage regulator; analog domain, see Analog ground Analog ground Analog ground Analog ground; Exposed paddle of QFN package AT86RF231 Section 9 ...
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... Analog and RF Pins 1.2.1 Supply and Ground Pins EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are controlled independently by the radio transceivers state machine and are activated dependent on the current radio transceiver state ...
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... Supply pins (voltage regulator output) for the digital 1.8V voltage domain, recommended bypass capacitor 1 µF. DC level at pin AVDD for various transceiver states Supply pin (voltage regulator output) for the analog 1.8V voltage domain, recommended bypass capacitor 1 µF. AT86RF231 Section 7. “Operating Modes” on Section 7.1.2.3 116. 117. ...
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... Digital Pins The AT86RF231 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Interface” on page Additional digital output signals DIG1...DIG4 are provided to control external blocks, i.e. for Antenna Diversity RF switch control RX/TX Indicator, see sity” ...
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... Value ( Reset values of register bits are underlined characterized in the document. 116. CLKM Driver Strength Value Section 9.6 “Crystal Oscillator (XOSC)” on page Section 9.6 “Crystal Oscillator (XOSC)” on page AT86RF231 CLKM_CTRL TRX_CTRL_0 R/W R/W R Description Section 9.6 “ ...
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... Overview The AT86RF231 is a feature rich, low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate 2.4 GHz ISM band applications. The radio transceiver is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip ...
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... The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed. The AT86RF231 block diagram is shown in Figure 4-1. AT86RF231 Block Diagram ext ...
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... An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the AT86RF231, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines. The AT86RF231 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing ...
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... Application Circuits 5.1 Basic Application Schematic A basic application schematic of the AT86RF231 with a single-ended RF connector is shown in Figure 5-1 on page RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required. Figure 5-1. RF The power supply decoupling capacitors (CB2, CB4) are connected to the external analog sup- ply pin (EVDD, pin 28) and external digital supply pin (DEVDD, pin 15) ...
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... Epcos B37920 AVX 06035A220JAT2A AVX 06035A229DA 2.2 pF Murata GRP1886C1H2R0DA01 0.47 pF 680Ω CX-4025 16 MHz ACAL Taitjen XWBBPL-F-1 SX-4025 16 MHz Siward A207-011 AT86RF231 Comment 2.45 GHz Balun 2.45 GHz Balun / Filter X5R 10% (0603) COG 5% (0603) COG 5% (0402 or 0603) COG ±0.5 pF (0603) Designed for f Depends on final PCB ...
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... The AT86RF231 supports additional features like: • • • • • An extended feature set application schematic illustrating the use of the AT86RF231 Extended Feature Set, see ure 5-2 on page is possible to use all features separately or in various combinations. Figure 5-2. Extended Feature Application Schematic ANT0 ...
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... DIG1/DIG2, the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the second RX/TX switch (SW1). During transmit the AT86RF231 TX signal is amplified using an external PA (N1) and fed to the antennas via an RF switch (SW2). In this example RF switch SW2 further supports Antenna Diversity controlled by the differential pin pair DIG1/DIG2 ...
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... Figure 6-1. Microcontrollers with a master SPI such as Atmel's AVR family interface directly to the AT86RF231. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 6-1 on page 16 Table 6-1. ...
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... MISO 8111C–MCU Wireless–09/09 Signal Description of Microcontroller Interface (Continued) Multipurpose control signal (functionality is state dependent, see -Sleep/Wakeup -TX start -disable/enable CLKM AT86RF231 reset signal, active low Optional, IRQ_2 (RX_START) for RX Frame Time Stamping, see and Figure 6-3 on page ...
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... MSB first. An SPI transaction is finished by releasing /SEL = H. An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in /SEL = L enables the MISO output driver of the AT86RF231. The MSB of MISO is valid after t1 (see Section 12.4 “Digital Interface Timing Characteristics” on page 157 is updated at each falling edge of SCLK ...
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... ADDRESS[5:0] MISO PHY_STATUS 1. Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for details refer to tion” on page 24. Figure 6-5 on page 20). AT86RF231 Access Mode Access Type Read access Register access Write access Read access Frame Buffer access Write access ...
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... XX Section 9.3 “Frame Buffer” on page 79. 21. 99. Figure 6-7 on page 20 byte 2 (data byte) byte 3 (data byte PHR[7:0] PSDU[7:0] AT86RF231 byte 2 (data byte) WRITE DATA[7:0] XX READ COMMAND XX PHY_STATUS READ DATA 107. An introduction Section 8.1 “Introduction - IEEE 802.15.4 - Figure 6-7 on page 20 Section 8.6 “Link Quality illustrates the packet structure of a Frame ...
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... PHR byte, PSDU data, and LQI byte frame_length [command byte, PHR byte, and PSDU data] and Figure 6-10 on page PHR PSDU 1 PSDU 2 AT86RF231 Figure 6-8 on page 21. byte n-1 (data byte) byte n (data byte) PSDU[7:0] PSDU[7:0] XX illustrate an example SPI sequence ...
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... Section 9.3 “Frame Buffer” on page Section 7.2.4 “TX_ARET_ON - Transmit with Automatic Retry and 64. 107. Figure 6-11 on page byte 2 (address) byte 3 (data byte) ADDRESS[6: DATA[7:0] AT86RF231 PSDU 3 PSDU 107. 154. Table 6-2 on 22). byte n-1 (data byte) byte n (data byte DATA[7:0] DATA[7:0] ...
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... ADDRESS[6:0] DATA[7: and Figure 6-14 on page DATA 1 DATA 2 DATA 1 DATA Section 6.2.2 “Frame Buffer Access Mode” on page AT86RF231 Figure 6-12 on page 23). byte n-1 (data byte) DATA[7:0] XX illustrate an example SPI sequence DATA 3 DATA 4 DATA 3 DATA 20). Section 9.3.3 “Interrupt Handling” on page ...
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... Radio Transceiver Status Information - PHY_STATUS Value Description 0 default (empty, all bits 0x00) 1 monitor TRX_STATUS register; see 2 monitor PHY_RSSI register; see 3 monitor IRQ_STATUS register; see Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page AT86RF231 IRQ_MASK_MODE IRQ_POLARITY R/W R/W R 147. 150. ...
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... Radio Transceiver Identification The AT86RF231 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID. 6.4.1 Register Description - AT86RF231 Identification Register 0x1C (PART_NUM): Bit +0x1C Read/Write Reset Value • ...
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... Description 0x1F Atmel JEDEC manufacturer ID, Bits [7: bit manufacturer ID MAN_ID_1[7: JEDEC Manufacturer ID - Bits [15:8] Value Description 0x00 Atmel JEDEC manufacturer ID, Bits [15: bit manufacturer ID AT86RF231 MAN_ID_1 26 ...
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... AT86RF231 can be powered down to reduce the overall power consumption. A power-down scenario is shown in TRX_OFF state the microcontroller forces the AT86RF231 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 clock cycles. This enables a microcontroller in a synchronous system to complete its power-down rou- tine and prevent deadlock situations ...
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... RX_ON and RX_AACK_ON states For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF231 supports an additional power-down mode for receive operating states (RX_ON and RX_AACK_ON incoming frame is expected and no other applications are running on the microcontroller, it can be powered down without missing incoming frames ...
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... Interrupt Logic 6.6.1 Overview The AT86RF231 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a sepa- rate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ, pin 24) ...
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... Wireless–09/09 67. Section 11.7 “Frame Buffer Empty Indicator” on page 152 MASK_AMI MASK_CCA_ED_DONE MASK_TRX_END R/W R/W R AMI CCA_ED_DONE TRX_END AT86RF231 Section 7.2.5 “Interrupt Han MASK MASK MASK _RX_START _PLL_UNLOCK _PLL_LOCK R/W R/W R RX_START PLL_UNLOCK PLL_LOCK ...
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... Refer to • Bit [3:2] - SPI_CMD_MODE Refer to • Bit 1 - IRQ_MASK_MODE The AT86RF231 supports polling of interrupt events. Interrupt polling can be enabled by register bit IRQ_MASK_MODE. Even if an interrupt request is masked by the corresponding bit in regis- ter 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS). Table 6-10. Register Bit IRQ_MASK_MODE 8111C– ...
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... This setting does not affect the polarity of the Frame Buffer Empty Indicator, refer to 11.7 “Frame Buffer Empty Indicator” on page active high. 8111C–MCU Wireless–09/09 Table 6-11 on page Configuration of Pin 24 (IRQ) Value Description 0 pin IRQ high active 1 pin IRQ low active 152. The Frame Buffer Empty Indicator is always AT86RF231 32. Section 32 ...
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... Operating Modes 7.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of the AT86RF231, such as receiving and transmitting frames, the power up sequence and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and ISM applications; the corresponding radio transceiver states are shown in Figure 7-1 ...
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... A successful state change can be verified by reading the radio transceiver status from register 0x01 (TRX_STATUS). If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF231 state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Pin SLP_TR is a multifunctional pin, refer to (SLP_TR)” ...
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... Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control. Note that the analog front-end is disabled during TRX_OFF. 8111C–MCU Wireless–09/09 7. This is necessary to support microcontrollers where Table 7-1 on page 158, parameter 12.5.7), a valid SPI write access to register 117. Section 9.3 “Frame Buffer” on page 107 128). AT86RF231 Section 1.3.2 “Pull-Up 42. Section 12.5 Section 9.6.4 and Section 11.1 “Security Module 35 ...
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... RX_ON and BUSY_RX - RX Listen and Receive State In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled. The AT86RF231 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver cir- cuitry, which are always turned on ...
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... The radio transceiver only reenters the RX_ON_NOCLK state, when the next rising edge of pin SLP_TR pin occurs. If the AT86RF231 is in the RX_ON_NOCLK state, and pin SLP_TR is reset to logic low, it enters the RX_ON state, and it starts to supply clock on the CLKM pin again. ...
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... An overview about the register reset values is provided in 7.1.3 Interrupt Handling All interrupts provided by the AT86RF231 (see Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. On receive IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception ...
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... Section 12.4 “Digital Interface Timing Characteristics” on Power-on Procedure to P_ON State 0 100 P_ON XOSC, DVREG t TR1 ) is firstly supplied to the AT86RF231, the radio trans 330 µs (typ.), the master clock signal is available at pin 17 TR1 AT86RF231 192+(9+m)*32 IRQ_3 (TRX_END MHR FCS ...
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... TR2 Transmission from TRX_OFF to PLL_ON and RX_ON State 0 TRX_OFF AVREG PLL PLL_ON t TR4 If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately, even if the PLL has not settled. AT86RF231 Figure 7-4 on page 40. 400 200 IRQ_4 (AWAKE_END) TRX_OFF FTN XOSC, DVREG Figure 7-5 on page 100 ...
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... TX_START. The PLL set- tles to the transmit frequency and the PA is enabled µs after initiating the transmission the AT86RF231 changes into BUSY_TX state and TR10 the internally generated SHR is transmitted. After that the PSDU data are transmitted from the Frame Buffer ...
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... If the radio transceiver was in SLEEP state, the XOSC and DVREG are enabled before entering TRX_OFF state. If register TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initial- ization until the AT86RF231 reaches TRX_OFF, do not try to initiate a further state change while the radio transceiver is in this state. Notes • ...
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... AT86RF231 41. The worst case values include maximum oper- Comment Leaving SLEEP state, depends on crystal Q factor and load capacitor FTN tuning time fixed Depends on external bypass capacitor at DVDD (CB3 = 1 µF nom., 10 µF worst case), depends on V Depends on external bypass capacitor at AVDD (CB1 = 1 µ ...
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... Section 8.5 “Clear Channel Assessment (CCA)” on page Section 8.5 “Clear Channel Assessment (CCA)” on page Table 7-1 on page 42. AT86RF231 Section 7.2 “Extended TRX_STATUS 94. 94 ...
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... BUSY_RX_AACK_NOCLK (2) 0x1F STATE_TRANSITION_IN_PROGRESS All other values are reserved 1. Extended Operating Mode only, refers not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state SLEEP state register not accessible. AT86RF231 Section 7.2 “Extended Operating Mode” on page 47. 45 ...
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... TX_ARET_ON All other values are reserved and mapped to NOP 1. FORCE_PLL_ON is not valid for states SLEEP, P_ON, RESET, TRX_OFF, and all *_NOCLK states, as well as STATE_TRANSITION_IN_PROGRESS towards these states. 2. Extended Operating Mode only, refers to ters” on page 68. AT86RF231 Section 7.2 “Extended TRX_CMD R/W R/W ...
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... FCS is valid, and if the sequence number of the ACK matches the sequence number of the previously transmitted frame. Dependent on the value of the frame pending subfield in the received acknowledgement frame the transaction status is set, see An AT86RF231 state diagram including the Extended Operating Mode states is shown in 7-8 on page represent the Extended Operating Mode. ...
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... TRX_OFF 12 (Clock State) XOSC=ON Pull=OFF RX_ON RX_ON (Rx Listen State) PLL_ON 9 From / To TRX_OFF RX_AACK_ON RX_AACK_ ON_NOCLK CLKM=OFF AT86RF231 SLEEP (Sleep State) XOSC=OFF Pull=OFF 3 (from all states) /RST = L 13 /RST = H RESET (all modes except P_ON) 4 SLP_TR=H or TX_START 10 PLL_ON BUSY_TX 11 (PLL State) ...
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... TX_START to register bits TRX_CMD. The TX_ARET state is left by writing the command TRX_OFF or PLL_ON to the register bits TRX_CMD. If the AT86RF231 is within a CSMA-CA, a frame-transmit or an acknowledgment procedure (BUSY_TX_ARET) the state change is executed after finish. Alternatively the com- mand FORCE_TRX_OFF or FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into radio transceiver state TRX_OFF or PLL_ON, respectively ...
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... The register bits MAX_CSMA_RETRIES (register 0x2C) configure the number of CSMA-CA retries after a busy channel is detected. 8111C–MCU Wireless–09/09 Section 7.1 “Basic Operating Mode” on page Section 7.2.3.1 “Description of RX_AACK Configuration Bits” on page Section 8.5) AT86RF231 registers 0x20 - 0x2B registers 0x2C, 0x2E registers 0x17, 0x2E 54. register 0x04, TRX_CTRL_1 register 0x2C, XAH_CTRL_0 ...
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... PAN-ID and IEEE address). Frame filtering as described in page 61 During reception the AT86RF231 parses bit [5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an ACK reply is expected. In that case and if the frame passes the third level of filtering, see IEEE 802.15.4-2006, section 7.5.6.2, the radio transceiver automatically generates and transmits an ACK frame ...
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... The status of the RX_AACK operation is indicated by register bits TRAC_STATUS (register 0x02, TRAC_STATUS), see 68. During the operations described above the AT86RF231 remains in BUSY_RX_AACK state. 8111C–MCU Wireless–09/09 Section 7.2.7 “Register Description - Control Registers” on page AT86RF231 52 ...
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... ACK requested (see Note Slotted Operation == AACK_ACK_TIME == Wait 12 symbol Wait 2 symbol periods periods N Transmit ACK TRX_STATE = RX_AACK_ON AT86RF231 Promiscuous Mode Reserved Frames Frame reception N AACK_PROM_MODE == FCF[2:0] > AACK_UPLD_RES_FT == FCS valid Y Generate IRQ_3 Generate IRQ_3 ...
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... All registers mentioned in mary” on page Note, that the general behavior of the "AT86RF231 Extended Feature Set", “AT86RF231 Extended Feature Set” on page 8111C–MCU Wireless–09/09 summarizes all register bits which affect the behavior of an RX_AACK ...
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... IEEE_ADDR_0 ........ IEEE_ADDR_7 7 RX_SAFE_MODE 0 SLOTTED_OPERATION 7:6 AACK_FVN_MODE AT86RF231 Description Set node addresses 0: disable frame protection 1: enable frame protection 0: if transceiver works in unslotted mode 1: if transceiver works in slotted mode Controls the ACK behavior, depending on FCF frame version number 0x00: acknowledges only frames with version number 0, i ...
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... SLOTTED_OPERATION 3 AACK_I_AM_COORD 5 AACK_SET_PD 7:6 AACK_FVN_MODE Figure 7-9 on page 53. According to IEEE 802.15.4-2006 when in promiscuous AT86RF231 56. Description Set node addresses 0: disable frame protection 1: enable frame protection 0: if transceiver works in unslotted mode 1: if transceiver works in slotted mode 1: device is PAN coordinator 0: frame pending subfield is not set in FC ...
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... IEEE_ADDR_7 1 AACK_PROM_MODE 4 AACK_DIS_ACK 7:6 AACK_FVN_MODE 85). According to the promiscuous mode definition the AT86RF231 Description Address shall be set: 0x00 1: Enable promiscuous Mode 1: Disable generation of acknowledgment Controls the ACK behavior, depending on FCF frame version number 0x00: acknowledges only frames with version number 0, i.e. according to IEEE 802.15.4-2003 ...
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... IEEE_ADDR_0 ........ IEEE_ADDR_7 7 RX_SAFE_MODE 4 AACK_UPLD_RES_FT 5 AACK_FLTR_RES_FT 0 SLOTTED_OPERATION AT86RF231 54, should be set to their reset values. Description 1: Enable promiscuous Mode 1: Disable generation of acknowledgment Section 8.1.2.2 “Frame Control Description Set node addresses 0: disable frame protection 1: enable frame protection 1: Enable reserved frame type reception Filter reserved frame types like data frame type, ...
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... Wireless–09/09 RX_AACK Configuration to Receive Reserved Frame Types (Continued) 3 AACK_I_AM_COORD 4 AACK_DIS_ACK 7:6 AACK_FVN_MODE AT86RF231 0: device is not PAN coordinator 1: device is PAN coordinator 0: Enable generation of acknowledgment 1: Disable generation of acknowledgment Controls the ACK behavior, depending on FCF frame version number 0x00: acknowledges only frames with version number 0, i ...
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... Data Rate Modes” on page 7.2.3.4 RX_AACK_NOCLK - RX_AACK_ON without CLKM If the AT86RF231 is listening for an incoming frame and the microcontroller is not running an application, the microcontroller can be powered down to decrease the total system power con- sumption. This special power-down scenario for systems running in clock synchronous mode (see Section 6. “ ...
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... IRQ_5 (AMI) a filtering pro- cedure as described in IEEE 802.15.4-2006, section 7.5.6.2 (Third level of filtering) is applied to the frame. The AT86RF231 RX_AACK mode accepts only frames that satisfy all of the following requirements (quote from IEEE 802.15.4-2006, section 7.5.6.2): 1 ...
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... RX_AACK Mode Timing A timing example of an RX_AACK transaction is shown in ple a data frame of length 10 with an ACK request is received. The AT86RF231 changes to state BUSY_RX_AACK after SFD detection. The completion of the frame reception is indicated by a TRX_END interrupt. Interrupts IRQ_2 (RX_START) and IRQ_5 (AMI) are disabled in this exam- ple. The ACK frame is automatically transmitted after a default wait period of 12 symbols (192 µ ...
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... If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, an acknowledgment frame is sent already 2 symbol times after the reception of the last symbol of a data or MAC command frame. 8111C–MCU Wireless–09/09 512 Data Frame (Length = 10, ACK=1) SFD BUSY_RX_AACK RX TRX_END t IRQ 192 µs (12 symbols) AT86RF231 704 1088 time [µs] ACK Frame RX_AACK_ON ...
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... MAX_CSMA_RETRIES Result Success Transmit Frame frame_rctr = frame_rctr + 1 N ACK requested Y N Receive ACK until timeout Y Y ACK valid N N frame_rctr > Data Pending MAX_FRAME_RETRIES Y TRAC_STATUS = TRAC_STATUS = NO_ACK SUCCESS_DATA_PENDING Issue IRQ_3 (TRX_END) interrupt AT86RF231 N csma_rctr > TRAC_STATUS = TRAC_STATUS = SUCCESS CHANNEL_ACCESS_FAILURE TRX_STATE = TX_ARET_ON 64 ...
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... Overview The implemented TX_ARET algorithm is shown in In TX_ARET mode, the AT86RF231 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4-2006, section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply ...
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... Here an example data frame of length 10 with an ACK request is transmitted, see page 67. After that the AT86RF231 switches to receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait for ACK and ACK receive the radio transceiver status register TRX_STATUS (register 0x01, TRX_STATUS) signals BUSY_TX_ARET ...
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... Section 7.2.3.5 “Frame Filtering” on page 61 38. The use of the other interrupts is optional. Section 7.2.3.5 “Frame Filtering” on page Section 6.6 “Interrupt Logic” on page AT86RF231 38. The microcontroller enables interrupts by Section 7.1.3 “Interrupt Handling” 61, and the completion of 29, are also available in ...
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... CSMA-CA seed value, RX_AACK control CSMA_BE CSMA-CA back-off exponent control Reserved Section 8.5 “Clear Channel Assessment (CCA)” on page Section 8.5 “Clear Channel Assessment (CCA)” on page AT86RF231 Section 8.5.6 Section 8.5 TRX_STATUS 94, not updated in Extended 94, not updated in Extended ...
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... TRX_STATUS Notes: Register 0x02 (TRX_STATE): The AT86RF231 radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. A successful state transition shall be confirmed by reading register bits TRX_STATUS (register 0x01, TRX_STATUS) ...
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... NOP 0x02 TX_START 0x03 FORCE_TRX_OFF (1)(2) 0x04 FORCE_PLL_ON 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) 0x16 RX_AACK_ON 0x19 TX_ARET_ON All other values are reserved and mapped to NOP AT86RF231 and RX_AACK acknowledgement. Slotted acknowledgement must be enabled with Section 7.2.4 64. TX_ARET ...
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... Section 8.2 “Frame Check Sequence (FCS)” on page Section 11.7 “Frame Buffer Empty Indicator” on page Section 6.3 “Radio Transceiver Status information” on page Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page AACK_UPLD_RES_FT Reserved R/W R AT86RF231 IRQ_MASK_MODE IRQ_POLARITY R/W R/W R 147. 150. 85. 152. ...
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... Here frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1). • Bit 0 - Reserved 8111C–MCU Wireless–09/09 137. Section 7.2.3.6 “RX_AACK Slotted Operation - Slotted Acknowledgement” on AT86RF231 Section 11.3 “High Data Rate 72 ...
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... Register Bit Slotted Acknowledgement Operation Value State Description 0 The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested. 1 Refer to Section acknowledgement frame has to be controlled by the microcontroller CSMA_SEED_0[7:0] R/W R/W R/W R AT86RF231 SLOTTED_OPERATION R/W R/W R 7.2.3.6. The transmission R/W R/W R/W R ...
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... Bit [7:6] - AACK_FVN_MODE The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK_FVN_MODE specifies the frame filtering behavior of the AT86RF231. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. ...
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... CCA. For details refer to IEEE 802.15.4- 2006, Section 7.5.1.4. Valid values are [MAX_BE, (MAX_BE - 1), … , 4'd0]. Note • If MIN_BE = 0 and MAX_BE = 0 the CCA back off period is always set to 0. 8111C–MCU Wireless–09/ R/W R/W R AT86RF231 [1] might change the MIN_BE R/W R/W R CSMA_BE 75 ...
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... SHORT_ADDR_0[7:0] R/W R/W R/W R SHORT_ADDR_1[7:0] R/W R/W R/W R PAN_ID_0[7:0] R/W R/W R/W R PAN_ID_1[7:0] R/W R/W R/W R AT86RF231 R/W R/W R/W R SHORT_ADDR_1 R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R SHORT_ADDR_0 PAN_ID_0 PAN_ID_1 ...
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... IEEE_ADDR_0[7:0] R/W R/W R/W R IEEE_ADDR_1[7:0] R/W R/W R/W R IEEE_ADDR_2[7:0] R/W R/W R/W R IEEE_ADDR_3[7:0] R/W R/W R/W R AT86RF231 R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R IEEE_ADDR_0 IEEE_ADDR_1 IEEE_ADDR_2 IEEE_ADDR_3 ...
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... IEEE_ADDR_4[7:0] R/W R/W R/W R IEEE_ADDR_5[7:0] R/W R/W R/W R IEEE_ADDR_6[7:0] R/W R/W R/W R IEEE_ADDR_7[7:0] R/W R/W R/W R AT86RF231 R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R IEEE_ADDR_4 IEEE_ADDR_5 IEEE_ADDR_6 IEEE_ADDR_7 ...
Page 79
... IEEE 802.15.4 compliant frames. On receive the PHR is returned as the first octet during Frame Buffer read access. Even though the standard only defines frame lengths ≤127 bytes, AT86RF231 is able to transmit and receive frame length values >127. For IEEE 802.15.4 compliant operation bit 7 has to be masked by SW ...
Page 80
... Request PAN Frame Control Field 2 octets Frame ACK Intra Reserved Pending Request PAN Frame Control Field 2 octets AT86RF231 Payload Reserved MPDU (Acknowledgement) Reserved MPDU MAC Payload MAC Service Data Unit (MSDU) Auxiliary Security Header 0/5/6/10/14 octets Destination ...
Page 81
... This subfield is used for address filtering by the third level filter rules. Only frame types pass the third level filter rules, refer to filtering by the AT86RF231 is enabled when using the RX_AACK mode, refer to “RX_AACK_ON - Receive with Automatic ACK” on page However, a reserved frame (frame type value > 3) can be received if register bit AACK_UPLD_RES_FT (register 0x17, XAH_CTRL_1) is set, for details refer to “ ...
Page 82
... PAN-ID of the source address field is omitted. In RX_AACK mode, this bit is evaluated by the address filter logic of the AT86RF231. • Bit [11:10]: the "Destination Addressing Mode" subfield describes the format of the destination address of the frame ...
Page 83
... Bit [15:14]: the "Source Addressing Mode" subfield, with similar meaning as "Destination Addressing Mode", see Table 8-3 on page The subfields of the FCF (Bits 0- 10-15) affect the address filter logic of the AT86RF231 while operating in RX_AACK operation, see matic ACK” on page 8.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 All unsecured frames according to IEEE 802 ...
Page 84
... This is the actual MAC payload usually structured according to the individual frame type. A description can be found in IEEE 802.15.4-2006, section 5.5.3.2. 8.1.2.8 MAC Footer (MFR) Fields The MAC footer consists of a two-octet Frame Checksum (FCS), for details refer to “Frame Check Sequence (FCS)” on page 8111C–MCU Wireless–09/09 AT86RF231 85. Section 8.1.2.3 83, is set Section 8.2 84 ...
Page 85
... MSDU fields). The frame check sequence has a length of 16 bit and is located in the last two bytes of a frame (MAC footer, see The AT86RF231 applies an FCS check on each received frame. The FCS check result is stored in register bit RX_CRC_VALID in register 0x06 (PHY_RSSI). ...
Page 86
... Automatic FCS generation The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1 (reset value). This allows the AT86RF231 to compute the FCS autonomously. For a frame with a frame length specified ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer ...
Page 87
... Section 11.6 “RX Frame Time Stamping” on page Section 11.7 “Frame Buffer Empty Indicator” on page Section 6.3 “Radio Transceiver Status information” on page Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page RX_CRC_VALID RND_VALUE AT86RF231 IRQ_MASK_MODE IRQ_POLARITY R/W R/W R 147. 150. 152. 24. ...
Page 88
... RX_CRC_VALID • Bit [6:5] - RND_VALUE Refer to register description in • Bit [4:0] - RSSI Refer to register description in 8111C–MCU Wireless–09/09 RX Frame FCS Check Value State Description 0 FCS is not valid 1 FCS is valid Section 11.2.2 “Register Description” on page Section 8.3.4 “Register Description” on page AT86RF231 136. 90. 88 ...
Page 89
... The RSSI value is a 5-bit value indicating the receive power, in steps and with a range 28. An RSSI value of 0 indicates a receiver RF input power of P the range 28, the RF input power can be calculated as follows RSSI_BASE_VAL + 3 RF 8111C–MCU Wireless–09/09 91. 91. (RSSI -1) [dBm] * AT86RF231 Section 8.4 Section 8.4 “Energy Detec- < -91 dBm. For an RSSI value ...
Page 90
... Ideal RX_CRC_VALID RND_VALUE Section 8.2.5 “Register Description” on page Section 11.2.2 “Register Description” on page < -91 dBm (see parameter 12.7.16), a value power of RF AT86RF231 RSSI RSSI ...
Page 91
... Wireless–09/ µs due to the length of the SHR. Including the ED TR27 Register Bit PHY_ED_LEVEL Interpretation Description 0xFF Reset value 0x00.... 0x54 ED measurement result of the last ED measurement AT86RF231 137. For manually initiated ED measurements = 140 µs (128 µs measurement duration and pro- TR26 91 ...
Page 92
... Data Interpretation The PHY_ED_LEVEL is an 8-bit register. The ED value of the AT86RF231 has a valid range from 0x00 to 0x54 with a resolution of 1 dB. All other values do not occur; a value of 0xFF indi- cates the reset value. A value of PHY_ED_LEVEL = 0 indicates that the measured energy is less than -91 dBm (see parameter 12.7.16 RSSI_BASE_VAL, teristics” ...
Page 93
... RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. 8111C–MCU Wireless–09/ ED_LEVEL[7: 137. For manually initiated ED measurements in AT86RF231 PHY_ED_LEVEL ...
Page 94
... The CCA modes are configurable via register 0x08 (PHY_CC_CCA). Using the Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the AT86RF231 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS) ...
Page 95
... Table 8-9 on page 95. CCA Measurement Period and Access in BUSY_RX state Request within ED measurement Energy above threshold. CCA result is available after finishing automated ED measurement period. Carrier sense only. CCA result is immediately available after request. AT86RF231 (1) Request after ED measurement CCA result is immediately available after request. 95 ...
Page 96
... After receiving the SHR an automated ED measurement is started with a length of 8 symbol periods (PSDU rate 250 kb/s), refer to automated ED measurement must be finished to provide a result for the CCA measurement. Only one automated ED measurement per frame is performed. AT86RF231 CCA result is immediately available after request. CCA result is immediately available after request. Section 8.4 “ ...
Page 97
... State Description 0 CCA calculation not finished 1 CCA calculation finished CCA Status Result Value State Description 0 Channel indicated as busy 1 Channel indicated as idle Section 7.1.5 “Register Description” on page 44 68 CCA_MODE R/W R AT86RF231 2 1 TRX_STATUS and Section 7.2.7 “Register Descrip CHANNEL R/W R/W R ...
Page 98
... Mode 3a, Carrier sense OR energy above threshold 1 Mode 1, Energy above threshold 2 Mode 2, Carrier sense only 3 Mode 3b, Carrier sense AND energy above threshold for logical operation OR, and for logical operation AND. Section 9.7 “Frequency Synthesizer (PLL)” on page R/W R/W R AT86RF231 121 CCA_ED_THRES R/W R/W R CCA_THRES 98 ...
Page 99
... Overview The LQI measurement of the AT86RF231 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames ...
Page 100
... High LQI values indicate a sufficient high signal power and low signal distortions. Note, the received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the AT86RF231 do not characterize the signal quality and the ability to decode a signal example, a received signal with an input power of about 6 dB above the receiver sensitiv- ity likely results in a LQI value close to 255 for radio channels with very low signal distortions ...
Page 101
... Module Description 9.1 Receiver (RX) 9.1.1 Overview The AT86RF231 receiver is split into an analog radio front end and a digital base band proces- sor (RX BBP), see Figure 9-1. RFP RFN The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF) ...
Page 102
... IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the Extended Operating Mode requires further register configurations, for details refer to The AT86RF231 receiver has an outstanding sensitivity performance of -101 dBm. At certain environmental conditions or for High Data Rate Modes, refer to Modes” on page adjusting the synchronization header detector threshold using register bits RX_PDT_LEVEL (register 0x15, RX_SYN) ...
Page 103
... R R Receiver Desensitization Threshold Level - RX_PDT_LEVEL RX Input Threshold Level ≤ RSSI_BASE_VAL (reset value) 0x0 0x1 > RSSI_BASE_VAL + ... 0xE > RSSI_BASE_VAL + 0xF > RSSI_BASE_VAL + parameter 12.8.4. AT86RF231 RX_PDT_LEVEL R/W R/W R Table 9-1 on page 103 Value [dBm] RSSI value not considered > -90 > -51 > -48 Section 12.8 “ ...
Page 104
... Transmitter (TX) 9.2.1 Overview The AT86RF231 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-2. DIG3/4 RFP RFN The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in section 6.5.2. The O-QPSK modula- tion signal is generated and fed into the analog radio front end ...
Page 105
... Register Bits PA_BUF_LT 8111C–MCU Wireless–09/ BUSY_TX PA_BUF_LT PA_LT R/W R/W R Buffer Enable Time Relative to the PA Value AT86RF231 PA_LT Section 11.5 “RX/TX Indicator” on page TX_PWR R/W R/W R Section 11.5. PA Buffer Lead Time [µ ...
Page 106
... These register bits control the enable lead time of the internal PA relative to the beginning of the transmitted frame. Table 9-3. Register Bits PA_LT • Bit [3:0] - TX_PWR These register bits determine the TX output power of the AT86RF231. Table 9-4. Register Bits TX_PWR 8111C–MCU Wireless–09/09 PA Enable Time Relative to the Start of the Frame (SHR) ...
Page 107
... Frame Buffer The AT86RF231 contains a 128 byte dual port SRAM. One port is connected to the SPI inter- face, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep one IEEE 802 ...
Page 108
... User accessible Frame Content The AT86RF231 supports an IEEE 802.15.4 compliant frame format as shown in page 108. Figure 9-4. AT86RF231 Frame Structure Length [octets] 0 Frame Preamble Sequence Duration 4 octets / 128 µs SHR not accesible Access PHY generated Notes: A frame comprises two sections, the radio transceiver internally generated SHR field and the user accessible part stored in the Frame Buffer ...
Page 109
... PHY data rate to ensure no under run interrupt. The first byte of the PSDU data must be available in the Frame Buffer before SFD transmission is complete, which takes 176 µs (16 µs PA ramp up + 160 µs SHR) from the rising edge of SLP_TR pin (see 2 on page 8111C–MCU Wireless–09/09 152. 39). AT86RF231 Section 11.7 Figure 7- 109 ...
Page 110
... Configurable for usage of external voltage regulator 9.4.1 Overview The internal voltage regulators supply a stabilized voltage to the AT86RF231. The AVREG pro- vides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. A simplified schematic of the internal voltage regulator is shown in Figure 9-5 ...
Page 111
... Analog voltage regulator disabled or supply voltage not stable 1 Analog supply voltage has settled Regulated Voltage Supply Control for Digital Building Blocks Value Description 0 Internal voltage regulator enabled, digital section 1 Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section AT86RF231 DVDD_OK Reserved R R/W R ...
Page 112
... DVREG is active. So this bit is normally always read out as 1. • Bit [1:0] - Reserved 8111C–MCU Wireless–09/09 Regulated Voltage Supply Control for Digital Building Blocks Value Description 0 Digital voltage regulator disabled or supply voltage not stable 1 Digital supply voltage has settled AT86RF231 112 ...
Page 113
... Note, the battery monitor is inactive during P_ON and SLEEP states, see status register 0x01 (TRX_STATUS). 8111C–MCU Wireless–09/09 Simplified Schematic of BATMON EVDD DAC Threshold Voltage For input-to-output mapping see control register 0x11 (BATMON) AT86RF231 Figure 9-6 on page 113. BATMON_OK + - „1“ clear D Q BATMON_IRQ ...
Page 114
... Description 0 The battery voltage is below the threshold. 1 The battery voltage is above the threshold. Battery Monitor Range Selection Value Description 0 Enables the low range, see BATMON_VTH 1 Enables the high range, see BATMON_VTH AT86RF231 29. Note that the interrupt is issued only BATMON_VTH R/W R/W R ...
Page 115
... Battery Monitor Threshold Voltage Value Voltage [V] BATMON_HR = 1 0x0 2.550 0x1 2.625 0x2 2.700 0x3 2.775 0x4 2.850 0x5 2.925 0x6 3.000 0x7 3.075 0x8 3.150 0x9 3.225 0xA 3.300 0xB 3.375 0xC 3.450 0xD 3.525 0xE 3.600 0xF 3.675 AT86RF231 Voltage [V] BATMON_HR = 0 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 115 ...
Page 116
... Configurable clock output (CLKM) 9.6.1 Overview The crystal oscillator generates the reference frequency for the AT86RF231. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. There- fore, the overall system performance is mainly determined by the accuracy of crystal reference frequency ...
Page 117
... Pins” on page 8111C–MCU Wireless–09/ TRIM PAR decreases with increasing crystal load capacitor values. TRIM Figure 9-8 on page 117 and the register bits XTAL_MODE (register 0x12, Setup for Using an External Frequency Reference 16 MHz XTAL1 7. AT86RF231 XTAL2 PCB AT86RF231 Section 1.3 “Digital 117 ...
Page 118
... CLKM Driver Strength Value Description CLKM Clock Rate Update Scheme Value Description 0 CLKM clock rate change appears immediately 1 CLKM clock rate change appears after SLEEP cycle AT86RF231 37, register bits CLKM_CTRL are 2 1 CLKM_CTRL R/W R TRX_CTRL_0 R/W 1 118 ...
Page 119
... MHz 6 250 kHz 7 62.5 kHz (IEEE 802.15.4 symbol rate R/W R/W R Crystal Oscillator Operating Mode Value Description 0x4 Internal crystal oscillator disabled, use external reference frequency 0xF Internal crystal oscillator enabled XOSC voltage regulator enabled AT86RF231 XTAL_TRIM R/W R/W R XOSC_CTRL 119 ...
Page 120
... XTAL2. A capacitance value in the range from 4 selectable with a resolution of 0.3 pF. Table 9-16. Register Bit XTAL_TRIM 8111C–MCU Wireless–09/09 Crystal Oscillator Trimming Capacitors Value Description 0x0 0.0 pF, trimming capacitors disconnected 0x1 0.3 pF trimming capacitor switched on ... 0xF 4.5 pF trimming capacitor switched on AT86RF231 120 ...
Page 121
... Fast PLL settling to support frequency hopping 9.7.1 Overview The PLL generates the RF frequencies for the AT86RF231. During receive operation the fre- quency synthesizer works as a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal ...
Page 122
... Bit [4:0] - CHANNEL The register bits CHANNEL define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. 8111C–MCU Wireless–09/ CCA_MODE R/W R Section 8.5 “Clear Channel Assessment (CCA)” on page Section 8.5 “Clear Channel Assessment (CCA)” on page AT86RF231 CHANNEL R/W R/W R 94. 94. ...
Page 123
... Reserved R/W R/W R µs (typ.). The register bit is cleared immediately after finishing the calibration Reserved R/W R/W R AT86RF231 Center Frequency [MHz] 2405 2410 2415 2420 2425 2430 2435 2440 2445 2450 2455 2460 2465 2470 2475 2480 R/W R/W ...
Page 124
... Bit 7 - PLL_DCU_START PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after at most t ing the calibration. • Bit [6:0] - Reserved 8111C–MCU Wireless–09/ µs, the register bit is set to 0. The register bit is cleared immediately after finish- TR22 AT86RF231 124 ...
Page 125
... Bit 7 - FTN_START FTN_START = 1 initiates the filter tuning network calibration. When the calibration cycle has fin- ished after at most 25 µs the register bit is automatically reset to 0. • Bit [6:0] - Reserved 8111C–MCU Wireless–09/09 10 Reserved R/W R/W R AT86RF231 FTN_CTRL R/W R/W R 125 ...
Page 126
... Radio Transceiver Usage This section describes basic procedures to receive and transmit frames using the AT86RF231. For a detailed programming description refer to reference [6]. 10.1 Frame Receive Procedure A frame reception comprises of two actions: The PHY listens for, receives and demodulates the frame to the Frame Buffer and signalizes the reception to the microcontroller. After or while that the microcontroller read the available frame data from the Frame Buffer via the SPI interface ...
Page 127
... TX_START to register 0x02 (TRX_STATE), while the radio transceiver is in state PLL_ON or TX_ARET_ON. The completion of the transac- tion is indicated by interrupt IRQ_3 (TRX_END). Figure 10-2. Transaction between AT86RF231 and Microcontroller during Transmit Alternatively a frame transmission can be started first, followed by the Frame Buffer write access (PSDU data); refer to ...
Page 128
... Overview The security module is based on an AES-128 core according to FIPS197 standard, refer to [5]. The security module works independent of other building blocks of the AT86RF231, encryption and decryption can be performed in parallel to a frame transmission or reception. Controlling the security block is implemented as an SRAM access to address space 0x82 to 0x94 ...
Page 129
... AES operation. This initial key is used for the next AES run even it cannot be read from AES_KEY. Note • ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The AT86RF231 provides this functionality as an additional feature. 11.1.4 Security Operation Modes 11.1.4.1 Electronic Code Book (ECB) ECB is the basic operating mode of the security module ...
Page 130
... Addresses 0x94: start AES operation, ECB mode Plaintext Encryption Block Cipher Key Encryption Ciphertext Ciphertext Decryption Block Cipher Key Decryption Plaintext AT86RF231 byte 18 (data) byte 19 (AES cmd) data_15[7: Section 6.2.3 Figure 11-2 on page 130. Figure 11-3 on page 130 Plaintext Encryption Block Cipher Key ...
Page 131
... Wireless–09/09 Figure 11-4 on page Plaintext Initialization Vector (IV) Encryption Block Cipher Key Encryption Ciphertext ECB mode Section 11.1.4 “Security Operation Modes” on page 129 AT86RF231 131. This mode is used for the Plaintext Encryption Block Cipher Key Encryption Ciphertext CBC mode Figure 11-4 on page 131. ...
Page 132
... Characteristics” on page the transfer of the data via the SPI interface. To reduce the overall processing time the AT86RF231 provides a Fast SRAM access for the address space 0x82 to 0x94. Figure 11-5. Packet Structure - Fast SRAM Access Mode ...
Page 133
... AES_MODE = Contains AES_STATE (128-bit data block) CTRL AES_ _MIRROR Mirror of register 0x83 (AES_ Reserved, not available 22. Note, that the SRAM register are reset when Reserved AT86RF231 Section 12.4 “Digital CTRL ) AES_DONE AES_STATUS 133 ...
Page 134
... AES Core Status Value Description 0 Security module, AES core idle 1 Write access: Start security module AES Mode Value Description 0 ECB mode, refer to Section 11.1.4.1 1 KEY mode, refer to Section 11.1.3 2 CBC mode, refer to Section 11.1.4 Reserved AT86RF231 Reserved AES_CTRL 134 ...
Page 135
... This register could be used to start a security operation within a single SRAM access by append- ing it to the data stream and setting register bit AES_REQUEST = 1. 8111C–MCU Wireless–09/09 AES Direction Value Description 0 AES encryption (ECB, CBC) 1 AES decryption AES_MODE AES_DIR R/W R/W R AT86RF231 Reserved AES_CTRL 135 ...
Page 136
... Random Number Generator 11.2.1 Overview The AT86RF231 incorporates a 2-bit truly random number generator by observation of noise. This random number can be used to: • Generate random seeds for CSMA-CA algorithm • Generate random values for AES key generation The random number is updated every t values are stored in register bits RND_VALUE (register 0x06, PHY_RSSI). ...
Page 137
... Reduced ACK timing (optional) 11.3.1 Overview The AT86RF231 also supports alternative data rates, higher than 250 kb/s for applications beyond IEEE 802.15.4 compliant networks. The selection of a data rate does not affect the remaining functionality. Thus it is possible to run all features and operating modes of the radio transceiver in various combinations. ...
Page 138
... Wireless–09/09 832 1472 2000 1000 500 250 2000 kb/s 1000 kb PSDU length in octets Section 6.2.2 “Frame Buffer Access Mode” on page AT86RF231 Figure 11-7 on page 500 kb/s 250 kb 100 2752 time [µs] 138. 120 20. However, 138 ...
Page 139
... XX XX PHR[7:0] PSDU[7:0] Section 12.8 “Current Consumption Specifications” on page 161 Section 9.1.4 “Register Description” on page 51, the acknowledgment frame response time can be reduced to illustrates an example for a reception and acknowledgement of AT86RF231 byte n-1 (data byte) byte n (data byte PSDU[7:0] ED[7:0] Section 8.4 “Energy Detection (ED)” on 138 ...
Page 140
... PSDU: 80 octets PSDU: 80 octets Reserved Section 11.8.2 “Register Description” on page OQPSK Data Rate Value OQPSK Data Rate AT86RF231 704 916 192 µs ACK ACK 32 µ OQPSK_DATA_RATE R R/W R 154. Comment 250 kb/s IEEE 802.15.4 compliant ...
Page 141
... Refer to • Bit 0 - Reserved 8111C–MCU Wireless–09/ AACK_UPLD_RES_FT Reserved R/W R 7.2.7 “Register Description - Control Registers” on page Section 7.2.7 “Register Description - Control Registers” on page Section 7.2.7 “Register Description - Control Registers” on page AT86RF231 AACK_ACK_TIME AACK_PROM_MODE Reserved R/W R 68. 68. 68. XAH_CTRL_1 R 0 ...
Page 142
... Antenna Diversity The Antenna Diversity implementation is characterized by: • Improves signal path robustness between nodes • AT86RF231 self-contained antenna diversity algorithm • Direct register based antenna selection 11.4.1 Overview Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small changes of the antenna location. These fading effects can result in an increased error floor or loss of the connection between devices ...
Page 143
... Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bit ANT_CTRL. If the AT86RF231 is not in a receive or transmit state recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1/DIG2 are pulled-down to digital ground ...
Page 144
... Reset value used if Antenna Diversity algorithm is disabled 0x3 Recommended correlator threshold for Antenna Diversity operation Other Reserved Reserved ANT_DIV_EN Section 11.4.2 “Antenna Diversity Application Example” on page Value Description 0 Antenna 0 1 Antenna 1 AT86RF231 ANT_EXT_SW_EN ANT_CTRL R/W R/W R ANT_DIV 144 ...
Page 145
... Stamping” on page If the register bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states as long as register bit ANT_EXT_SW_EN is set. If the AT86RF231 is not in a receive or transmit state recommended to disable register bit ANT_EXT_SW_EN to reduce the power con- sumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital ground ...
Page 146
... Table 11-14. Antenna Diversity Switch Control ANT_CTRL Note: 8111C–MCU Wireless–09/09 0 Reserved 1 Antenna 1 DIG1 = L DIG2 = H 2 Antenna 0 DIG1 = H DIG2 = L 3 Default value for ANT_EXT_SW_EN = 0. Mandatory setting for applications not using Antenna Diversity. Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1. AT86RF231 146 ...
Page 147
... This differential pin pair can be used to control PA, LNA, and RF switches. If the AT86RF231 is not in a receive or transmit state recommended to disable register bit PA_EXT_EN (register 0x04, TRX_CTRL_1) to reduce the power consumption or avoid leakage current of external RF switches and other building blocks, especially during SLEEP state ...
Page 148
... RF switches or other building blocks, especially during SLEEP state. Section 11.6 “RX Frame Time Stamping” on page Section 8.2 “Frame Check Sequence (FCS)” on page Section 11.7 “Frame Buffer Empty Indicator” on page Section 6.3 “Radio Transceiver Status information” on page AT86RF231 104 IRQ_MASK_MODE IRQ_POLARITY ...
Page 149
... Bit 1 - IRQ_MASK_MODE Refer to • Bit 0 - IRQ_POLARITY Refer to 8111C–MCU Wireless–09/09 Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page AT86RF231 29. 29. 149 ...
Page 150
... Wireless–09/09 Figure 11-3 on page 128 160 192 SFD PHR Preamble RX_ON Timing figures refer to 12.4 “Digital Interface Timing Characteristics” on page AT86RF231 130. 192 + < 128 PSDU (250 kb/s) BUSY_RX IRQ_2 (RX_START) t IRQ Time [µs] RX_ON TRX_END t IRQ 157. ...
Page 151
... Section 11.5 “RX/TX Indicator” on page Figure 11-12 on page Section 8.2 “Frame Check Sequence (FCS)” on page Section 11.7 “Frame Buffer Empty Indicator” on page Section 6.3 “Radio Transceiver Status information” on page Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page AT86RF231 2 1 IRQ_MASK_MODE IRQ_POLARITY R/W R/W ...
Page 152
... SPI bus until the Frame Command XX XX PHR[7:0] PSDU[7:0] PSDU[7:0] Frame Buffer Empty Indicator t 13 (1) (2) (3) = 750 nsec after the rising edge of last SCLK clock of the Frame Buffer 13 AT86RF231 PSDU[7:0] LQI[7:0] IRQ_3 (TRX_END) (4) Command XX PHY_STATUS IRQ_STATUS 152 ...
Page 153
... Section 6.2 “SPI Protocol” on page Value Description 0 Frame Buffer Empty Indicator disabled 1 Frame Buffer Empty Indicator enabled Section 6.3 “Radio Transceiver Status information” on page Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page AT86RF231 2 1 IRQ_MASK_MODE IRQ_POLARITY R/W R 147. 150. ...
Page 154
... Dynamic Frame Buffer Protection 11.8.1 Overview The AT86RF231 continues the reception of incoming frames as long any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Pro- ...
Page 155
... To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled an IRQ_2 (RX_START) is issued only if the received SFD matches the register content of register SFD_VALUE and a valid PHR is received. 8111C–MCU Wireless–09/ SFD_VALUE[7:0] R/W R/W R/W R AT86RF231 R/W R/W R/W R [1] SFD_VALUE and [2]. This 155 ...
Page 156
... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Condition T = 10s, (soldering profile compliant with IPC/JEDEC J STD 020B) Compl. to [3], Compl. to [4] Condition Voltage on pins 15, 28 External voltage supply on pins (2) 13, 14, 29 AT86RF231 Min. Typ. -50 5000 1500 -0.3 -0.3 Min. Typ. -40 (1) 1.8 3.0 1 ...
Page 157
... SPI read/write, standard SRAM and Frame Buffer access modes, Idle time between consecutive SPI accesses SPI Fast SRAM read/write access mode, refer to Section Idle time between consecutive SPI accesses 10 clock cycles at 16 MHz 10 clock cycles at 16 MHz AT86RF231 Min. Typ. Max V - 0 0.4 DD ...
Page 158
... OQPSK_DATA_RATE = 1 OQPSK_DATA_RATE = 2 OQPSK_DATA_RATE = 3 As specified in [1], [2] Reference oscillator Leaving SLEEP state to clock available at pin 17 (CLKM) PSDU bit rate 250 kb/s PSDU bit rate 500 kb/s PSDU bit rate 1000 kb/s PSDU bit rate 2000 kb/s AT86RF231 750 250 62.5 (Min.) increases to 450 ns. ...
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... Condition Maximum configurable TX output power value Register bit TX_PWR = 0 16 steps, configurable in register 0x05 (PHY_TX_PWR) 100Ω differential impedance dBm TX Complies with EN 300 328/440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210 AT86RF231 Figure 5-1 on page 12. Min. Typ. Max Units dBm 20 dB ±3 ...
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... Offset freq. interf MHz Offset freq. interf MHz At maximum gain Offset freq. interf MHz Offset freq. interf MHz Tolerance within gain step Defined as RSSI_BASE_VAL ≤ RSSI_BASE_VAL > RSSI_BASE_VAL + AT86RF231 Fig- Min. Typ. Max Units -101 dBm -97 dBm -95 dBm -89 ...
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... OP (1) Condition dBm dBm -17 dBm TX RX_ON state - high input level RX_ON state - high sensitivity RX_ON state, with register setting (2) RX_PDT_LEVEL > 0 PLL_ON state TRX_OFF state SLEEP state Condition AT86RF231 Figure 5-1 on page Min. Typ. Max 14 11.6 7.4 10.3 12.3 11.8 5.6 0.4 0. Min. Typ. Max 16 8 ...
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... Typical Characteristics 13.1 Active Supply Current The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement setup used for the measurements ...
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... Figure 13-2. Current Consumption in TRX_OFF State 13.1.2 PLL_ON state Figure 13-3. Current Consumption in PLL_ON State 8111C–MCU Wireless–09/09 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 EVDD [ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 85 °C 25 °C 0 °C -40 °C 3.8 85 °C 25 °C 0 °C -40 °C 3.8 163 ...
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... Figure 13-4. Current Consumption in RX_ON State - High Sensitivity Figure 13-5. Current Consumption in RX_ON State - High Input Level 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 85 °C 25 °C 0 °C -40 °C 3.8 85 °C 25 °C 0 °C -40 °C 3.8 164 ...
Page 165
... Figure 13-6. Current Consumption in RX_ON State - Reduced Sensitivity 13.1.4 TX_BUSY state Figure 13-7. Current Consumption in TX_BUSY State - Minimum Output Power 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 85 °C 25 °C 0 °C -40 °C 3.8 85 °C 25 °C 0 °C -40 °C 3.8 165 ...
Page 166
... Figure 13-8. Current Consumption in TX_BUSY State - Output Power 0 dBm Figure 13-9. Current Consumption in TX_BUSY State - Maximum Output Power 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 85 °C 25 °C 0 °C -40 °C 3.8 85 °C 25 °C 0 °C -40 °C 3.8 166 ...
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... Figure 13-10. Current Consumption in SLEEP 13.2 State Transition Timing Figure 13-11. Transition Time from EVDD to P_ON (CLKM available) 8111C–MCU Wireless–09/09 1000 100 10 1 0.1 1.6 1.8 2.0 2.2 2.4 500 450 400 350 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 EVDD [V] 2.6 2.8 3.0 3.2 3.4 3.6 EVDD [V] 85 °C 25 °C -40 °C 3.8 85 °C 25 °C 0 °C -40 °C 3.8 167 ...
Page 168
... Figure 13-12. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)) Figure 13-13. Transition Time from TRX_OFF to PLL_ON 8111C–MCU Wireless–09/09 500 450 400 350 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 EVDD [V] 140 120 100 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 85 °C 25 °C 0 °C -40 °C 3.8 85 °C 25 °C 0 °C -40 °C 3.8 168 ...
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... Register Summary The AT86RF231 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: Addr Name Bit7 Bit6 0x00 - - 0x01 TRX_STATUS CCA_DONE CCA_STATUS 0x02 TRX_STATE TRAC_STATUS[2] TRAC_STATUS[1] 0x03 TRX_CTRL_0 PAD_IO[1] PAD_IO[0] 0x04 TRX_CTRL_1 PA_EXT_EN IRQ_2_EXT_EN 0x05 ...
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... CSMA_SEED_0 CSMA_SEED_0[7] CSMA_SEED_0[6] 0x2E CSMA_SEED_1 AACK_FVN_MODE[1] AACK_FVN_MODE[0] 0x2F CSMA_BE MAX_BE[3] MAX_BE[2] .... - - The reset values of the AT86RF231 registers in state P_ON page 170. Note: Table 14-1. Register Summary - Reset Values Address Reset Value Address 0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x19 0x04 ...
Page 171
... Electrostatic discharge - Error vector magnitude - Frame control field - Frame check sequence - First in first out - Filter tuning network - General purpose input output - Industrial, scientific, and medical - Low-drop output - Low-noise amplifier - Local oscillator - Link quality indicator - Least significant bit - Medium access control AT86RF231 171 ...
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... Radio frequency - Received signal strength indicator - Receiver - SPI Interface: SPI clock - SPI Interface: SPI select - Start-of-frame delimiter - Synchronization header - Serial peripheral interface - Static random access memory - Single side band filter - Transmitter - Voltage controlled oscillator - Voltage regulator - Crystal oscillator AT86RF231 172 ...
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... Wireless–09/09 Voltage Range Temperature Range 1.8V - 3.6V Industrial (-40° +85° C) Lead-free/Halogen-free 1.8V - 3.6V Industrial (-40° +125° C) Lead-free/Halogen-free T&R quantity 5,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. Thermal Resistance Velocity [m/ 2.5 AT86RF231 Theta ja [K/W] 40.9 35.7 32.0 173 ...
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... Wireless–09/09 D Pin 1 Corner Pin 1 Corner A2 A2 Pin 1 Corner Pin 1 Corner SYMBOL TITLE 32QN2, 32-lead 5.0 x 5.0 mm Body, 0.50 mm Pitch, Quad Flat No Lead Package (QFN) Sawn AT86RF231 Side View Side View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE D 5.00 BSC E 5 ...
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... Appendix A - Continuous Transmission Test Mode 20.1 Overview The AT86RF231 offers a Continuous Transmission Test Mode to support final application / pro- duction tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode continuous wave signal (CW mode). ...
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... Enable Continuous Transmission Test Mode - step # 3 0x09 Enable PLL_ON state 0x01 Wait for IRQ_0 (PLL_LOCK) 0x02 Initiate Transmission, enter BUSY_TX state Perform measurement 0x00 Disable Continuous Transmission Test Mode Reset AT86RF231 Comment modulated RF signal f - 0.5 MHz, CW signal 0.5 MHz, CW signal CH 176 ...
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... Bit [3:0] - TST_CTRL_DIG These register bits enable continuous transmission: Table 20-3. Register Bit TST_CTRL_DIG 8111C–MCU Wireless–09/ R/W R/W R Continuous Transmission Value Description 0x0 Continuous Transmission disabled 0xF Continuous Transmission enabled 0x1 - 0xE Reserved AT86RF231 TST_CTRL_DIG R/W R/W R TST_CTRL_DIGI 177 ...
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... Introduction Appendix B contains information specific to devices operating at temperatures up to 125°C. Only deviations to the standard device AT86RF231-ZU are covered in this appendix, all other infor- mation are similar to previous sections. Performance figures for 125°C are only valid for device part number AT86RF231-ZF. ...
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... Typical Characteristics The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing for all supply voltages and all temperatures. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. Power consumption for the microcontroller required to program the radio transceiver is not included in the measurement results ...
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... Figure 21-2. Current Consumption in TRX_OFF State 21.4.2 PLL_ON state Figure 21-3. Current Consumption in PLL_ON State 8111C–MCU Wireless–09/09 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 EVDD [ 1.6 1.8 2.0 2.2 2.4 2.6 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.8 3.0 3.2 3.4 3.6 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 180 ...
Page 181
... Figure 21-5. Current Consumption in RX_ON State - High Input Level 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 181 ...
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... TX_BUSY state Figure 21-7. Current Consumption in TX_BUSY State - Minimum Output Power 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 182 ...
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... Figure 21-8. Current Consumption in TX_BUSY State - Output Power 0 dBm Figure 21-9. Current Consumption in TX_BUSY State - Maximum Output Power 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 EVDD [V] 2.6 2.8 3.0 3.2 3.4 3.6 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 125 °C 85 °C 25 °C 0 °C -40 °C 3.8 183 ...
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... SLEEP Figure 21-10. Current Consumption in SLEEP 8111C–MCU Wireless–09/09 10000 1000 100 10 1 0.1 1.6 1.8 2.0 2.2 2.4 AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 EVDD [V] 125 °C 85 °C 25 °C -40 °C 3.8 184 ...
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... Figure 21-12. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)) 8111C–MCU Wireless–09/09 500 450 400 350 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 EVDD [V] 500 450 400 350 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 125 °C -40 °C 85 °C 25 °C 3.8 125 °C -40 °C 85 °C 25 °C 3.8 185 ...
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... Figure 21-13. Transition Time from TRX_OFF to PLL_ON 8111C–MCU Wireless–09/09 140 120 100 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 -40 °C 25 °C 85 °C 125 °C 3.8 186 ...
Page 187
... Figure 21-15. Adjacent and Alternate Channel Selectivity 8111C–MCU Wireless–09/09 -89 -91 -93 -95 -97 -99 -101 -103 -105 1.6 1.8 2.0 2.2 2 -25 -20 -15 -10 -5 Channel Offset [MHz] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 EVDD [ 125 °C 85 °C 25 °C -40 °C 3.8 125 °C 85 °C 25 °C -40 °C 25 187 ...
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... RSSI Figure 21-16. RSSI 8111C–MCU Wireless–09/ -100 -90 -80 -70 -60 RX Input Level [dBm] AT86RF231 -50 -40 -30 -20 -10 -40 °C 25 °C 85 °C 125 °C 0 188 ...
Page 189
... Figure 21-18. TX Output Power vs. EVDD (TX_PWR = 0, CH=19) 8111C–MCU Wireless–09/ -10 -12 -14 -16 -18 - TX_PWR [Register Value] 4 3.5 3 2.5 2 1.5 1 0.5 0 1.6 1.8 2.0 2.2 2.4 AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 EVDD [V] -40 °C 25 °C 85 °C 125 °C 15 -40 °C 25 °C 85 °C 125 °C 3.8 189 ...
Page 190
... TX Output Power vs. Channel Figure 21-19. TX Output Power vs. Channel (EVDD = 3.0V, TX_PWR = 0) 8111C–MCU Wireless–09/09 4 3.5 3 2.5 2 1 Channel acct. IEEE802.15.4 AT86RF231 -40 °C 25 °C 85 °C 125 °C 27 190 ...
Page 191
... TX EVM vs. EVDD Figure 21-20. Error Vector Magnitude (EVM) vs. EVDD (TX_PWR = 0, CH=19) 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 125 °C 85 °C 25 °C -40 °C 3.8 191 ...
Page 192
... Appendix C - Errata 22.1 AT86RF231 Rev.A No known errata 8111C–MCU Wireless–09/09 AT86RF231 192 ...
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... Rev.8111A - 05/08 1. Initial revision 8111C–MCU Wireless–09/09 Updated the datasheet with a new device Added “Appendix B - AT86RF231-ZF Extended Temperature Range” on page 178 Editorial updates. Updated figures and graphics in sections: 5.,6., 8.,9.,11., 12.and Changed register and sub-register names in Editorial changes. AT86RF231 AT86RF231-ZF. 13. ...
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... Human Body Model (HBM). ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing - Charged Device Model (CDM). NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 AT86RF231 Software Programming Model AT86RF231 194 ...
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... Sleep/Wake-up and Transmit Signal (SLP_TR) ..............................................27 6.6 Interrupt Logic ..................................................................................................29 7.1 Basic Operating Mode .....................................................................................33 7.2 Extended Operating Mode ...............................................................................47 8.1 Introduction - IEEE 802.15.4 - 2006 Frame Format ........................................79 8.2 Frame Check Sequence (FCS) .......................................................................85 8.3 Received Signal Strength Indicator (RSSI) .....................................................89 8.4 Energy Detection (ED) .....................................................................................91 8.5 Clear Channel Assessment (CCA) ..................................................................94 8.6 Link Quality Indication (LQI) ............................................................................99 9.1 Receiver (RX) ................................................................................................101 9.2 Transmitter (TX) ............................................................................................104 AT86RF231 i ...
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... Radio Transceiver Usage .................................................................... 126 11 AT86RF231 Extended Feature Set ...................................................... 128 12 Electrical Characteristics .................................................................... 156 13 Typical Characteristics ........................................................................ 162 14 Register Summary ............................................................................... 169 15 Abbreviations ....................................................................................... 171 8111C–MCU Wireless–09/09 9.3 Frame Buffer ..................................................................................................107 9.4 Voltage Regulators (AVREG, DVREG) .........................................................110 9.5 Battery Monitor (BATMON) ...........................................................................113 9.6 Crystal Oscillator (XOSC) ..............................................................................116 9.7 Frequency Synthesizer (PLL) ........................................................................121 9 ...
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... Ordering Information ........................................................................... 173 17 Soldering Information .......................................................................... 173 18 Package Thermal Properties ............................................................... 173 19 Package Drawing - 32QN2 ................................................................... 174 20 Appendix A - Continuous Transmission Test Mode ......................... 175 21 Appendix B - AT86RF231-ZF Extended Temperature Range ........... 178 22 Appendix C - Errata ............................................................................. 192 23 Revision history ................................................................................... 193 References............................................................................................. 194 Table of Contents....................................................................................... i 8111C–MCU Wireless–09/09 20.1 Overview ........................................................................................................175 20 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...