AT89C51CC02 Atmel Corporation, AT89C51CC02 Datasheet - Page 2

• Manufacturer Part Number: AT89C51CC02
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC02

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 20
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 0.5
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

5. Timer 2 (Baud Rate Generator Mode) – Long Start Time
6. UART - RB8 Lost With JBC on SCON Register
7. CAN – CANCONCH Harmless Corruption
8. ADC - Interrupt Controller/ADC Idle Mode/Loops In High Priority Interrupt
9. Flash/EEPROM – First Read After Load Disturbed
10. CAN – Sporadic Errors
2
When Timer 2 is used as baud rate generator, TH2 is not loaded with RACP2H at the beginning, then UART is not
operational before almost 10,000 machine cycles.
Workaround
In the software add an initialization of TH2 and TL2, with the value of RCAP2H and RCAP2L.
When using the JBC instruction on any bit of SCON register, if RB8 changes from 1 to 0, the 0 bit can be lost.
Workaround
After each use clear RB8.
When a stuff error occurs during a CAN frame transmission on DPRAM write access, the CONCH1, CONCH0 bits in
CANCONCH are corrupted. This corruption has no effect on the correct behavior of the Transmit channel.
Workaround
No workaround required, re-writing CANCONCH to start a new message takes care of the corruption.
The problem occurs during an A/D conversion in idle mode, if a hardware interrupt occurs followed by a second inter-
rupt with higher priority before the end of the A/D conversion. If the above configuration occurs, the highest priority
interrupt is served immediately after the A/D conversion. At the end of the highest priority interrupt service, the proces-
sor will not serve the hardware reset interrupt pending. It will also not serve any new interrupt requests with a priority
lower than the high level priority last served.
Workaround
Disable all interrupts (Interrupt Global Enable Bit) before starting an A/D conversion in idle mode, then re-enable all
interrupts immediately after.
In the "In-Application Programming" mode from the Flash, if the User software application load the Column Latch Area
prior to call the programming sequence in the CAN Bootloader.
The "Read after load" issue leads to a wrong Opcode Fetch during the column latch load sequence.
Workaround
Update of the Flash API Library. A NOP instruction has to be inserted after the load instruction.
When BRP = 0 or when BRP > 0 and SMP = 0, the CAN controller may de synchronize and send one error frame to
ask for the retransmission of the incoming frame, even though it had no error.
This is likely to occur with BRP = 0 or after long inter frame periods without synchronization (low bus load). The CAN
macro can still properly synchronize on frames following the error.
Workaround
Setting BRP greater than 0 in CANBT1 and SMP equals 1 in CANBT3 allows re-synchronization with the majority vote,
and thus fixes the issue. The sampling point might have to be slightly advanced for the majority vote to take place
within the bit. Therefore, at maximum speed of 1Mbit/s, the sampling point should be at less than 80% (e.g. 75%) for
XTAL = 16MHz or less than 85% (e.g. 80%) for XTAL = 20 MHz.
T89C51CC02 Errata Sheet
MOVX @DPTR,A ;Load Column latches
NOP ; ADDED INSTRUCTION
4160F–CAN–05/06