AT89C51CC02 Atmel Corporation, AT89C51CC02 Datasheet - Page 3

• Manufacturer Part Number: AT89C51CC02
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC02

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 20
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 0.5
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

11. C51 Core
12. Timer0/1
13. Transmission after a 3 bit Intermessage
4160F–CAN–05/06
When exiting power-down mode by interrupt while CPU is in X2 mode, it leads to bad execution of the first instruction
run when CPU restarts.
Workaround
Set the CPU in X1 mode directly before entering power-down mode.
When the Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra interrupt may randomly occurred for
Timer0 or Timer1.
Workaround
Use the same mode for the two timers.
If a Transmit Message Object (MOB) is enabled while the CAN bus is busy with an on going message, the transmitter
will wait for the 3-bit Intermission before starting its transmission. This is in full agreement with the CAN
recommendation.
If the transmitter lost arbitration against another node, two conditions can occur :
1. At least one Receive MOB of the chip are programmed to accept the incoming message. In this case, the transmitter
will wait for the next 3-bit Intermission to retry its transmission.
2. No Receive MOB of the chip are programmed to accept the incoming message. In this case the transmitter will wait
for a 4-bit Intermission to retry its transmission. In this case, any other CAN nodes ready to transmit after a 3-bit Inter-
mission will start transmit before the chip transmitter, even if their messages have lower priority IDs.
Workaround
Always have a Receive MOB enabled ready to accept any incoming messages. Thanks to the implementation of the
CAN interface, a Receive MOB must be enable at latest, before the 1
register is written (RXOK if message OK) immediately after the 6
CAN2.0A mode a minimum 19-bit time delay to respond to the end of message interrupt (RXOK) and re-enable the
Receive MOB before the start of the DLC field of the next incoming message. This minimum delay will be 39-bit time in
CAN2.0B. See CAN2.0A CAN2.0B frame timings below.
–
–
Extra Interrupt
Bad Exit of Power-down in X2 Mode
th
T89C51CC02 Errata Sheet
-bit of the End Of Frame Field. This will leave in
st
bit of the DLC field. The Receive MOB status
3