AT89C51IC2 Atmel Corporation, AT89C51IC2 Datasheet - Page 72

• Manufacturer Part Number: AT89C51IC2
• Manufacturer: Atmel Corporation

Specifications of AT89C51IC2

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Baud Rate
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AT89C51IC2
drive the network. The Master may select each Slave device by software through port
pins (Figure 27). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•
•
Note:
In Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is
selected from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 56 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 56. SPI Master Baud Rate Selection
SPR2
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set
The Device is configured as a Slave with CPHA and SSDIS control bits set
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
0
0
0
0
1
1
1
1
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because
in this mode, the SS is used to start the transmission.
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
(1)
.
F
F
F
F
F
F
CLK PERIPH
Clock Rate
F
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
Don’t Use
CLK PERIPH
/128
/16
/32
/64
/8
/2
/4
Baud Rate Divisor (BD)
No BRG
128
16
32
64
2
4
8
4301D–8051–02/08
(2)
. This