AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet - Page 49

• Manufacturer Part Number: AT89LP4052
• Manufacturer: Atmel Corporation

Specifications of AT89LP4052

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 15
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI
• Watchdog: Yes

20. Analog Comparator
20.1
3547J–MICRO–10/09
Comparator Interrupt with Debouncing
A single analog comparator is provided on the AT89LP2052/LP4052. Comparator operation is
such that the output is a logic “1” when the positive input AIN0 (P1.0) is greater than the negative
input AIN1 (P1.1). Otherwise, the output is a zero. Setting the CEN bit in ACSR enables the
comparator. When the comparator is first enabled, the comparator output and interrupt flag are
guaranteed to be stable only after 10 µs. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before the interrupt
is enabled in order to prevent an immediate interrupt service. Before enabling the comparator
the analog inputs should be tri-stated by putting P1.0 and P1.1 into input-only mode. See
tion 15.5 “Port 1 Analog Functions” on page
The comparator output is internally tied to the P3.6 pin. Instructions which read the pins of P3
will also read the comparator output directly. Read-Modify-Write instructions or Write instructions
to P3.6 will access bit 6 of the Port 3 register without affecting the comparator.
The comparator may be configured to cause an interrupt under a variety of output value condi-
tions by setting the CM bits in ACSR. The comparator interrupt flag CF in ACSR is set whenever
the comparator output matches the condition specified by CM. The flag may be polled by soft-
ware or may be used to generate an interrupt and must be cleared by software. The EC bit in IE
must be set before CF will generate an interrupt.
The comparator output is sampled every clock cycle. The conditions on the analog inputs may
be such that the comparator output will toggle excessively. This is especially true if applying slow
moving analog inputs. Three debouncing modes are provided to filter out this noise. In debounc-
ing mode, the comparator uses Timer 1 to modulate its sampling time. When a relevant
transition occurs, the comparator waits until two Timer 1 overflows have occurred before resam-
pling the output. If the new sample agrees with the expected value, CF is set. Otherwise the
event is ignored. The filter may be tuned by adjusting the time-out period of Timer 1. Because
Timer 1 is free running, the debouncer must wait for two overflows to guarantee that the sam-
pling delay is at least 1 time-out period. Therefore after the initial edge event, the interrupt may
occur between 1 and 2 time-out periods later. See
By default the comparator is disabled during Idle mode. To allow the comparator to function dur-
ing Idle, the CIDL bit in ACSR must be set. When CIDL is set, the comparator can be used to
wake-up the CPU from Idle if the comparator interrupt is enabled. The comparator is always dis-
abled during Power-down mode.
Figure 20-1. Negative Edge with Debouncing Example
Timer 1 Overflow
Comparator Out
CF
Start
Compare
22.
Figure
Start
AT89LP2052/LP4052
20-1.
Compare
Sec-
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