AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 91

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

17. Enhanced Serial Peripheral Interface
3654A–MICRO–8/09
In a more complex system, the following could be used to select slaves 1 and 2 while excluding
slave 0:
Slave 0
Slave 1
Slave 2
In the above example, the differentiation among the 3 slaves is in the lower 3 address bits. Slave
0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that
bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and
its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2, use address
1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN.
Zeros in this result are treated as don’t cares. In most cases, interpreting the don’t cares as
ones, the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with
“0”s. This produces a given address of all “don’t cares” as well as a Broadcast address of all
“don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcon-
troller to use standard 80C51-type UART drivers which do not make use of this feature.
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
AT89LP428/828 and peripheral devices or between multiple AT89LP428/828 devices, including
multiple masters and slaves on a single bus. The SPI includes the following features:
A block diagram of the SPI is shown in
• Full-duplex, 3-wire or 4-wire Synchronous Data Transfer
• Master or Slave Operation
• Maximum Bit Frequency = f
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates or Timer 1-based Baud Generation (Master Mode)
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Double-buffered Receive and Transmit
• Transmit Buffer Empty Interrupt Flag
• Mode Fault (Master Collision) Detection and Interrupt
• Wake up from Idle Mode
SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
OSC
/4
Figure
17-1.
AT89LP428/828
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