AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet
AT89LP51ED2
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AT89LP51ED2 Summary of contents
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... Interrupt Priority • Nonvolatile Program and Data Memory – 64KB of In-System Programmable (ISP) Flash Program Memory – 4KB of EEPROM (AT89LP51ED2/ID2 Only) – 512-byte User Signature Array – Endurance: 10,000 Write/Erase Cycles – Serial Interface for Program Downloading – 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Bootloader • ...
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Pin Configurations 1.1 44-lead VQFP (†MOSI/CEX2/MISO) P1.5 1 (†MISO/CEX3/SCK) P1.6 2 (†SCK/CEX4/MOSI) P1.7 3 (DCL) RST 4 (RXD) P3.0 5 (SDA) P4.1 6 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 † ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary 1.5 Pin Description Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number (1) VQFP VQFN PLCC PDIP Symbol RST ...
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Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number (1) VQFP VQFN PLCC PDIP Symbol GND ...
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... The AT89LP51ID2 is not available in the PDIP package. 2. Overview The Atmel controller with 64KB of In-System Programmable Flash program memory. The AT89LP51ED2 and AT89LP51ID2 provide an additional 4KB of EEPROM for nonvolatile data storage. The devices are manufactured using Atmel's high-density nonvolatile memory technology and are compatible with the industry-standard 80C51 instruction set ...
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... The AT89LP51RD2/ED2/ID2 retains all of the standard features of the AT89C51RD2/ED2, including: 64KB of In-System Programmable Flash program memory, 4KB of EEPROM (AT89LP51ED2/ID2 Only), 256 bytes of RAM, 2KB of expanded RAM I/O lines, three 16-bit timer/counters, a Programmable Counter Array, a programmable hardware watchdog timer, a keyboard interface, a full-duplex enhanced serial port, a serial peripheral interface (SPI), on-chip crystal oscillator, and a four-level, ten-vector interrupt system ...
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... For more information, see the datasheet. 3714AS–MICRO–7/11 Atmel AT89LP51RD2/ED2/ID2 Block Diagram Flash Code Boot ROM EEPROM 64KB 2KB (AT89LP51ED2/ID2) 8051 Single Cycle CPU Port 0 Configurable I/O Port 1 Configurable I/O Port 2 Configurable I/O Port 3 Configurable I/O ...
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Table 2-1. Fuse Name Clock Source A Clock Source B Oscillator Select X2 Mode Start-up Time Compatibility Mode XRAM Configuration Bootloader Jump Bit On-Chip Debug Enable In-System Programming Enable User Signature Programming Enable Default Port State Low Power Mode 2.2.2 ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary 2.3 Comparison to the Atmel AT89C51RD2/ED2/ID2 The Atmel are fully binary compatible with the 8051 instruction set. The AT89LP51RD2/ED2/ID2 has two modes of operations, Compatibility mode and Fast mode. In Compatibility mode the instruction timing, peripheral ...
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Timer/Counters A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the WDT. The TPS defaults to 0101B, which causes the timers to count once every machine cycle. The counting rate ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary 2.3.9 Security The AT89LP51RD2/ED2/ID2 does not support the external access pin (EA). Therefore it is not possible to execute from external program memory in address range 0000H–1FFFH. When the third Lockbit is enabled (Lock Mode 4) ...
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Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary Table 3-2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer SPX EFh Extended Stack Pointer DPL 82h Data Pointer Low Byte DPH ...
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Table 3-5. Interrupt SFRs Mnemonic Add Name IEN0 A8h Interrupt Enable Control 0 IEN1 B1h Interrupt Enable Control 1 IPH0 B7h Interrupt Priority Control High 0 IPL0 B8h Interrupt Priority Control Low 0 IPH1 B3h Interrupt Priority Control High 1 ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary Table 3-8. Timer SFRs Mnemonic Add Name TCON 88h Timer/Counter 0 and 1 Control TMOD 89h Timer/Counter 0 and 1 Modes TCONB 91h Timer/Counter 0 and 1 Mode B TL0 8Ah Timer/Counter 0 Low Byte TH0 ...
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Table 3-11. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register KBMOD 9Fh Keyboard Mode Register Table 3-12. Flash/EEPROM Memory SFR Mnemonic Add Name BMSEL 92h Bank Mode ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary Table 3-15. PCA SFRs (Continued) Mnemo -nic Add Name CCAPM3 DDh PCA Timer/Counter Mode 3 CCAPM4 DEh PCA Timer/Counter Mode 4 CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 ...
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... Ordering Code AT89LP51RD2-20AAU AT89LP51RD2-20AAUR AT89LP51RD2-20AU AT89LP51RD2-20AUR No 1 AT89LP51RD2-20JU AT89LP51RD2-20JUR AT89LP51RD2-20MU AT89LP51RD2-20MUR AT89LP51RD2-20PU AT89LP51ED2-20AAU AT89LP51ED2-20AAUR AT89LP51ED2-20AU AT89LP51ED2-20AUR Yes 1 AT89LP51ED2-20JU AT89LP51ED2-20JUR AT89LP51ED2-20MU AT89LP51ED2-20MUR AT89LP51ED2-20PU AT89LP51ID2-20AAU AT89LP51ID2-20AAUR AT89LP51ID2-20AU Yes 2 AT89LP51ID2-20AUR AT89LP51ID2-20JU AT89LP51ID2-20JUR AT89LP51ID2-20MU Package Types Package Packing Tray 44AA (LQFP) Reel Tray 44A (TQFP) ...
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... AT89LP51RD2/ED2/ID2 Summary - Preliminary 4.2 Cross Reference with AT89C51RD2/ED2/ID2 Table 4-1. Ordering Cross Reference AT89C51RD2/ED2/ID2 to AT89LP51RD2/ED2/ID2 Device Migration AT89C51RD2 to AT89LP51RD2 AT89C51ED2 to AT89LP51ED2 AT89C51ID2 to AT89LP51ID2 Table 4-2. Packages Not Found in AT89C51RD2/ED2/ID2 Device AT89C51RD2 to AT89LP51RD2 AT89C51ED2 to AT89LP51ED2 AT89C51ID2 to AT89LP51ID2 3714AS–MICRO–7/11 Package Packing Previous Ordering Code ...
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Packaging Information 5.1 44AA – VQFP/LQFP PIN 1 PIN 1 IDENTIFIER e C 0°~8° L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary 5.2 44A – TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary 5.4 44M1 – VQFN/MLF D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 3714AS–MICRO–7/11 E Pin #1 ...
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PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed ...
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AT89LP51RD2/ED2/ID2 Summary - Preliminary 6. Revision History Revision No. Revision A – July 2011 3714AS–MICRO–7/11 History • Initial Release 25 ...
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