AT89S8253 Atmel Corporation, AT89S8253 Datasheet - Page 2
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AT89S8253
Manufacturer Part Number
AT89S8253
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89S8253.pdf
(60 pages)
2.AT89S8253.pdf
(2 pages)
3.AT89S8253.pdf
(2 pages)
4.AT89S8253.pdf
(2 pages)
Specifications of AT89S8253
Flash (kbytes)
12 Kbytes
Max. Operating Frequency
24 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Sram (kbytes)
0.25
Eeprom (bytes)
2048
Operating Voltage (vcc)
2.7 to 5.5
Timers
3
Isp
SPI
Watchdog
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89S8253-24AC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT89S8253-24AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT89S8253-24AU
Manufacturer:
ATMEL
Quantity:
6 250
Part Number:
AT89S8253-24AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT89S8253-24JC
Manufacturer:
ATMEL
Quantity:
5 530
Company:
Part Number:
AT89S8253-24JC
Manufacturer:
ATM
Quantity:
3 290
Company:
Part Number:
AT89S8253-24JC
Manufacturer:
ATMEL
Quantity:
6 988
Part Number:
AT89S8253-24JC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
2. Pin Configurations
2.1
2.2
2
40P6 – 40-lead PDIP
44A – 44-lead TQFP
AT89S8253
The AT89S8253 provides the following standard features: 12K bytes of In-System Programma-
ble Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer,
two data pointers, three 16-bit timer/counters, a six-vector, four-level interrupt architecture, a full
duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8253 is designed
with static logic for operation down to zero frequency and supports two software selectable
power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM
contents but freezes the oscillator, disabling all other chip functions until the next external inter-
rupt or hardware reset.
The on-board Flash/EEPROM is accessible through the SPI serial interface. Holding RESET
active forces the SPI bus into a serial programming interface and allows the program memory to
be written to or read from, unless one or more lock bits have been activated.
(MOSI) P1.5
(MISO) P1.6
(RXD) P3.0
(INT0) P3.2
(INT1) P3.3
(SCK) P1.7
(TXD) P3.1
(T0) P3.4
(T1) P3.5
(T2 EX) P1.1
(MOSI) P1.5
(MISO) P1.6
RST
(INT0) P3.2
(INT1) P3.3
(SCK) P1.7
(RXD) P3.0
(TXD) P3.1
NC
(WR) P3.6
(RD) P3.7
(SS) P1.4
(T2) P1.0
(T0) P3.4
(T1) P3.5
XTAL2
XTAL1
1
2
3
4
5
6
7
8
9
10
11
GND
P1.2
P1.3
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
33
32
31
30
29
28
27
26
25
24
23
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
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