AT90PWM2B Atmel Corporation, AT90PWM2B Datasheet - Page 25

• Manufacturer Part Number: AT90PWM2B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM2B

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.2
4317JS–AVR–08/10
AT90PWM2B/3B
15. PSC : Autolock mode
16. DALI : 17th bit detection
17. PSC : One ramp mode with PSC input mode 8
18. PSC : Desactivation of outputs in mode 14
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1. PSC : Double End-Of-Cycle Interrupt Request in Centered Mode
2. ADC : Conversion accuracy
3. DAC Driver linearity above 3.6V
The comparator output toggles at the comparator clock frequency when the voltage differ-
ence between both inputs is lower than the offset. This may occur when comparing signal
with small slew rate.
Work around:
This effect normally do not impact the PSC, as the transition is sampled once per PSC cycle
Be carefull when using the comparator as an interrupt source.
This mode is not properly handled when CLKPSC is different from CLK IO.
Work around:
With CLKPSC equals 64/32 MHz (CLKPLL), use LOCK mode
17th bit detection do not occurs if the signal arrives after the sampling point.
Workaround:
Use this feature only for sofware development and not in field conditions
The retriggering is not properly handled in this case.
Work around:
Do not program this case.
See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output” on
page 154.
Work around:
Do not use this mode to desactivate output if retrigger event do not occurs during On-Time.
PSC : Double End-Of-Cycle Interrupt Request in Centered Mode
ADC : Conversion accuracy
In centered mode, after the “expected” End-Of-Cycle Interrupt, a second unexpected Inter-
rupt occurs 1 PSC cycle after the previous interrupt.
Work around:
While CPU cycle is lower than PSC clock, the CPU sees only one interrupt request. For PSC
clock period greater than CPU cycle, the second interrupt request must be cleared by
software.
The conversion accuracy degrades when the ADC clock is 2 MHz.
Work around:
When a 10 bit conversion accuracy is required, use an ADC clock of 1 MHz or below.
At 2 Mhz the ADC can be used as a 7 bits ADC.
With 5V Vcc, the DAC driver linearity is poor when DAC output level is above Vcc-1V. At 5V,
DAC output for 1023 will be around 5V - 40mV.
Work around: .
AT90PWM2/3/2B/3B
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