ATmega168 Automotive Atmel Corporation, ATmega168 Automotive Datasheet - Page 252
ATmega168 Automotive
Manufacturer Part Number
ATmega168 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA168_AUTOMOTIVE.pdf
(19 pages)
3.ATMEGA168_AUTOMOTIVE.pdf
(340 pages)
Specifications of ATmega168 Automotive
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA168_AUTOMOTIVE PDF datasheet #2
- ATMEGA168_AUTOMOTIVE PDF datasheet #3
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21.6.3.2
21.6.4
252
ATmega48/88/168 Automotive
ADC Control and Status Register B – ADCSRB
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
• Bit 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bist
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
249.
ADC9
ADC1
15
R
R
7
0
0
R
7
–
0
ADC8
ADC0
ACME
R/W
14
R
R
6
0
0
6
0
ADC7
13
R
R
–
5
0
0
R
5
–
0
ADC6
12
R
R
–
4
0
0
R
4
–
0
ADC5
11
R
R
–
3
0
0
R
3
–
0
ADTS2
ADC4
R/W
10
R
R
–
2
0
0
2
0
“ADC Conversion Result” on
ADTS1
ADC3
R/W
R
R
9
–
1
0
0
1
0
ADTS0
ADC2
R/W
R
R
8
–
0
0
0
0
0
7530I–AVR–02/10
ADCSRB
.
ADCH
ADCL
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