ATmega324PA Atmel Corporation, ATmega324PA Datasheet - Page 19

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ATmega324PA

Manufacturer Part Number
ATmega324PA
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega324PA

Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8. AVR Memories
8.1
8.2
8272C–AVR–06/11
Overview
In-System Reprogrammable Flash Program Memory
T h i s s e c t i o n d e s c r i b e s t h e d i f f e r e n t m e m o r i e s i n t h e
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an EEPROM Memory for
data storage. All three memory spaces are linear and regular.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 16/32/64/128Kbytes
On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instruc-
tions are 16 or 32 bits wide, the Flash is organized as 32/64 x 16. For software security, the
Flash Program memory space is divided into two sections, Boot Program section and Applica-
tion Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Program Counter (PC) is 15/16
bits wide, thus addressing the 32/64K program memory locations. The operation of Boot Pro-
gram section and associated Boot Lock bits for software protection are described in detail in
”Memory Programming” on page
description on Flash data serial downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description.
Timing diagrams for instruction fetch and execution are presented in
ing” on page
15.
ATmega164A/PA/324A/PA/644A/PA/1284/P
297.
”Memory Programming” on page 297
”Instruction Execution Tim-
contains a detailed
19

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