ATmega325 Atmel Corporation, ATmega325 Datasheet - Page 15
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ATmega325
Manufacturer Part Number
ATmega325
Description
Manufacturer
Atmel Corporation
Specifications of ATmega325
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
20 000
Company:
Part Number:
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Part Number:
ATmega3250-16AI
Manufacturer:
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Quantity:
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Part Number:
ATmega3250-16AU
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Quantity:
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Part Number:
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7.8
2570N–AVR–05/11
Reset and Interrupt Handling
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 7-4.
Figure 7-5 on page 15
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 7-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming” on page 265
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see
251.
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
for details.
clk
clk
CPU
“Boot Loader Support – Read-While-Write Self-Programming” on page
CPU
shows the internal timing concept for the Register File. In a single clock
T1
T1
ATmega325/3250/645/6450
“Interrupts” on page 49
T2
T2
“Interrupts” on page
T3
T3
for more information.
“Memory Program-
49. The list also
T4
T4
15