ATmega3290A Atmel Corporation, ATmega3290A Datasheet - Page 252

• Manufacturer Part Number: ATmega3290A
• Manufacturer: Atmel Corporation

Specifications of ATmega3290A

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.5.4
8284D–AVR–6/11
LCDCCR – LCD Contrast Control Register
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation
is shown in
Table 24-6.
• Bits 7:5 – LCDDC[2:0]: LDC Display Configuration
The LCDDC[2:0] bits determine the amount of time the LCD drivers are turned on for each volt-
age transition on segment and common pins. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need longer drive time to achieve
satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD
clock period, even if the selected drive time is longer. When using static duty or blanking, drive
time will always be one half prescaled LCD clock period.
New values take effect immediately, and can cause small glitches in the display output. This can
be avoided by setting the LCDBL in LCDCRA, and wait to the next start of frame before chang-
ing LCDDC[2:0].
Table 24-7.
Note:
• Bit 4 – LCDMDT: LCD Maximum Drive Time
Writing this bit to one turns the LCD drivers on 100% all the time, regardless of the drive time
configured by LCDDC[2:0].
Bit
(0xE7)
Read/Write
Initial Value
clk
4MHz
4MHz
32.768kHz
32.768kHz
LCD
LCDDC2
The drive time will be longer dependent on oscillator startup time.
0
0
0
0
1
1
1
1
Table 24-6 on page
LCDDC2
Example of frame rate calculation
LCD Display Configuration
R/W
duty
7
0
Static
1/4
1/3
1/2
LCDDC1
R/W
K
8
6
8
8
6
0
LCDDC1
0
0
1
1
0
0
1
1
252.
LCDDC0
2048
2048
R/W
16
16
5
0
N
LCDNDT
R
4
0
LCDCD2:0
011
011
000
100
LCDDC0
LCDCC3
0
1
0
1
0
1
0
1
R/W
3
0
D
4
4
1
5
LCDCC2
R/W
2
0
Nominal drive time
300 µs
70 µs
150 µs
450 µs
575 µs
850 µs
1150 µs
50% of clk
Frame Rate
4000000/(8*2048*4) = 61Hz
4000000/(6*2048*4) = 81Hz
32768/(8*16*1) = 256Hz
32768/(8*16*5) = 51Hz
LCDCC1
R/W
1
0
LCD_PS
LCDCC0
R/W
0
0
LCDCCR
252