ATmega644PR231 Atmel Corporation, ATmega644PR231 Datasheet - Page 70

• Manufacturer Part Number: ATmega644PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega644PR231

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

10.2.6
10.2.7
10.2.8
8011O–AVR–07/10
PCMSK3 – Pin Change Mask Register 3
PCMSK2 – Pin Change Mask Register 2
PCMSK1 – Pin Change Mask Register 1
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 7:0 – PCINT31:24: Pin Change Enable Mask 31:24
Each PCINT31:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT31:24 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT31..24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23..16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit
(0x73)
Read/Write
Initial Value
Bit
(0x6D)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
PCINT31
PCINT23
PCINT15
R/W
R/W
R/W
7
0
7
0
7
0
PCINT30
PCINT22
PCINT14
R/W
R/W
R/W
6
0
6
0
6
0
PCINT29
PCINT21
PCINT13
R/W
R/W
R/W
5
0
5
0
5
0
PCINT28
PCINT20
PCINT12
R/W
R/W
R/W
4
0
4
0
4
0
ATmega164P/324P/644P
PCINT27
PCINT19
PCINT11
R/W
R/W
R/W
3
0
3
0
3
0
PCINT26
PCINT18
PCINT10
R/W
R/W
R/W
2
0
2
0
2
0
PCINT25
PCINT17
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
PCINT24
PCINT16
PCINT8
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK3
PCMSK2
PCMSK1
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