ATmega6450 Atmel Corporation, ATmega6450 Datasheet
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ATmega6450
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ATmega6450 Summary of contents
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... Up to 16MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory Segments – In-System Self-programmable Flash Program Memory • 32KBytes (ATmega325/ATmega3250) • 64KBytes (ATmega645/ATmega6450) – EEPROM • 1Kbytes (ATmega325/ATmega3250) • 2Kbytes (ATmega645/ATmega6450) – Internal SRAM • 2Kbytes (ATmega325/ATmega3250) • ...
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Pin Configurations Figure 1-1. Pinout ATmega3250/6450 1 DNC 2 (RXD/PCINT0) PE0 3 (TXD/PCINT1) PE1 4 (XCK/AIN0/PCINT2) PE2 5 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 6 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 9 (CLKO/PCINT7) PE7 10 VCC 11 GND 12 DNC 13 ...
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Figure 1-2. Pinout ATmega325/645 DNC 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) ...
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Overview The Atmel ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system ...
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CISC microcontrollers. The Atmel ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-Sys- tem Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte ...
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... Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450 The ATmega325, ATmega3250, ATmega645, and ATmega6450 differ only in memory sizes, pin count and pinout. devices. Table 2-1. Device ATmega325 ATmega3250 ATmega645 ATmega6450 2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. ...
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Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D ...
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Port J (PJ6..PJ0) Port 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capa- bility. As inputs, Port ...
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over ...
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Register Summary Note: Address Name Bit 7 Reserved - (0xFF) Reserved - (0xFE) Reserved - (0xFD) Reserved - (0xFC) Reserved - (0xFB) Reserved - (0xFA) Reserved - (0xF9) Reserved - (0xF8) Reserved - (0xF7) Reserved - (0xF6) Reserved - ...
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Address Name Bit 7 Reserved - (0xC3) UCSR0C - (0xC2) UCSR0B RXCIE0 (0xC1) UCSR0A RXC0 (0xC0) Reserved - (0xBF) Reserved - (0xBE) Reserved - (0xBD) Reserved - (0xBC) Reserved - (0xBB) USIDR (0xBA) USISR USISIF (0xB9) USICR USISIE (0xB8) Reserved ...
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Address Name Bit 7 TCNT1L (0x84) Reserved - (0x83) TCCR1C FOC1A (0x82) TCCR1B ICNC1 (0x81) TCCR1A COM1A1 (0x80) DIDR1 - (0x7F) DIDR0 ADC7D (0x7E) Reserved - (0x7D) ADMUX REFS1 (0x7C) ADCSRB - (0x7B) ADCSRA ADEN (0x7A) ADCH (0x79) ADCL (0x78) ...
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Address Name Bit 7 Reserved - 0x25 (0x45) TCCR0A FOC0A 0x24 (0x44) GTCCR TSM 0x23 (0x43) EEARH - 0x22 (0x42) EEARL 0x21 (0x41) EEDR 0x20 (0x40) EECR - 0x1F (0x3F) GPIOR0 0x1E (0x3E) EIMSK PCIE3 0x1D (0x3D) EIFR PCIF3 0x1C ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST ...
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Mnemonics Operands IN Rd Port OUT P, Rr Out Port PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 2570NS–AVR–05/11 ATmega325/3250/645/6450 Description ...
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Ordering Information 9.1 ATmega325 (3) Speed (MHz) Power Supply 8 1.8 - 5.5V 16 2.7 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information ...
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ATmega3250 (3) Speed (MHz) Power Supply 8 1.8 - 5.5V 16 2.7 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. ...
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ATmega645 (3) Speed (MHz) Power Supply 8 1.8 - 5.5V 16 2.7 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. ...
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... Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 2570NS–AVR–05/11 ATmega325/3250/645/6450 (2) Ordering Code Package Type ATmega6450V-8AU 100A (4) ATmega6450V-8AUR 100A ATmega6450-16AU 100A (4) ATmega6450-16AUR 100A and Figure 28-2 on page 299. Package Type (1) Operational Range Industrial 0°C to 85°C) (-4 20 ...
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Packaging Information 10.1 64A PIN 0°~7° Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...
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Marked Pin TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R ...
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PIN 0°~7° L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...
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Errata 11.1 Errata ATmega325 The revision letter in this section refers to the revision of the ATmega325 device. 11.1.1 ATmega325 Rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may ...
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... Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 11.4 Errata ATmega6450 The revision letter in this section refers to the revision of the ATmega6450 device. 11.4.1 ATmega6450 Rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer 1 ...
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Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 12.1 Rev. 2570N – 05/ 12.2 Rev. ...
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Rev. 2570I – 07/ 12.7 Rev. 2570H – 06/ 12.8 Rev. 2570G – 04/06 1. 12.9 Rev. 2570F – 03/06 1. 12.10 Rev. 2570E – 03/ ...
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Rev. 2570D – 05/ 12.12 Rev. 2570C – 11/ 12.13 Rev. 2570B – 09/04 1. 12.14 Rev. 2570A – 09/04 1. 2570NS–AVR–05/11 ...
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