ATtiny261 Automotive Atmel Corporation, ATtiny261 Automotive Datasheet - Page 70

• Manufacturer Part Number: ATtiny261 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny261 Automotive

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13. Timer/Counter0 Prescaler
13.0.1
13.0.2
70
ATtiny261/ATtiny461/ATtiny861
Prescaler Reset
External Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count
occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,
256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to
program execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the T0 synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects. See
Figure 13-1. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem).
CLK_I/O
/1024. See
Tn
clk
I/O
Table 13-1 on page 72
CLK_I/O
D
LE
ExtClk
Q
). Alternatively, one of four taps from the prescaler can be used as a
Table 13-1 on page 72
Synchronization
< f
D
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T
0
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
for details.
for details.
clk
D
CLK_I/O
I/O
). The latch is transparent in the
Q
Figure 13-1
/8, f
CLK_I/O
Edge Detector
/64, f
shows a functional
CLK_I/O
7753F–AVR–01/11
Tn_sync
(To Clock
Select Logic)
T0
/256, or
). The