ATtiny45 Atmel Corporation, ATtiny45 Datasheet
ATtiny45
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ATtiny45 Summary of contents
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... Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – Six Programmable I/O Lines – 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V) • Operating Voltage – 1.8 - 5.5V for ATtiny25V/45V/85V – 2.7 - 5.5V for ATtiny25/45/85 • ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up ATtiny25/45/85 2 PDIP/SOIC/TSSOP 1 8 VCC 2 7 PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2 PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) GND 4 5 PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) NOTE: TSSOP only for ATtiny45/V QFN/MLF 1 15 VCC 2 14 PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2 DNC DNC 4 12 DNC PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) 5 ...
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The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions ...
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Overview The ATtiny25/45/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny25/45/85 provides the following features: 2/4/8K ...
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About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. ...
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Register Summary Address Name Bit 7 0x3F SREG I 0x3E SPH – 0x3D SPL SP7 0x3C Reserved 0x3B GIMSK – 0x3A GIFR – 0x39 TIMSK – 0x38 TIFR – 0x37 SPMCSR – 0x36 Reserved 0x35 MCUCR BODS 0x34 MCUSR ...
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register SEC Set Carry ...
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Ordering Information 6.1 ATtiny25 (1) Speed (MHz) Supply Voltage (V) 10 1.8 – 5.5 20 2.7 – 5.5 Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green, and they comply ...
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... Industrial (4) (-40°C to +85°C) 8X 20M1 21.3 “Speed” on page 168. Package Types (2) (3) Ordering Code ATtiny45V-10PU ATtiny45V-10SU ATtiny45V-10SUR ATtiny45V-10SH ATtiny45V-10XU ATtiny45V-10XUR ATtiny45V-10MU ATtiny45V-10MUR ATtiny45-20PU ATtiny45-20SU ATtiny45-20SUR ATtiny45-20SH ATtiny45-20XU ATtiny45-20XUR ATtiny45-20MU ATtiny45-20MUR 2586NS–AVR–04/11 ...
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ATtiny85 (1) Speed (MHz) Supply Voltage (V) 10 1.8 – 5.5 20 2.7 – 5.5 Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European ...
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Packaging Information 7.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...
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Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. ...
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S8S1 Top View e Side View L End View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/ ...
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Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 2325 Orchard Parkway San Jose, CA 95131 R 2586NS–AVR–04/ ...
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D 1 Pin TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/85 18 ...
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... This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only. 8.1.3 Rev A Not sampled. 8.2 Errata ATtiny45 The revision letter in this section refers to the revision of the ATtiny45 device. 8.2.1 Rev F and G No known errata 8.2.2 Rev D and E • ...
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Rev B and C • PLL not locking • EEPROM read from application code does not work in Lock Bit Mode 3 • EEPROM read may fail at low supply voltage / low clock frequency • Timer Counter 1 ...
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The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / Workaround – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power ...
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Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 8.3.1 Rev B and C No known errata. 8.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock ...
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... Bandgap Voltage vs Section 25.1 “ATtiny25” on page page 209 and Section 25.2 “ATtiny45” on page 210 “Features” on page 1, removed Preliminary from ATtiny25 Section 8.4.2 “Code Example” on page 46 “PCMSK – Pin Change Mask Register” on page “TCCR1 – Timer/Counter1 Control Register” on page 92 Timer/Counter1 Control Register” ...
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Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]. 9.4 Rev. 2586K-01/08 1. Updated Document Template. 2. Added Sections: – – – 3. Updated Sections: – – – – – – – – – – ...
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... ADTS[2:0]: ADC Auto Trigger Source” on page 142 “SPMCSR – Store Program Memory Control and Status Register” on page “Errata ATtiny25” on page 217 “Errata ATtiny45” on page 217 “Errata ATtiny85” on page 220 “ATtiny25” on page 209 “ATtiny45” on page 210 “ ...
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Rev. 2586I-09/ ATtiny25/45/85 26 Updated “Bit 0” in “PRR ...
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Rev. 2586H-06/ 9.8 Rev. 2586G-05/ 10. 11. 9.9 Rev. 2586F-04/ 9.10 Rev. 2586E-03/ ...
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... TOV1: Timer/Counter1 Overflow Flag” on page Updated values in “DC Characteristics” on page Updated “Register Summary” on page Updated “Ordering Information” on page Updated Rev B and C in “Errata ATtiny45” on page All references to power-save mode are removed. Updated Register Adresses. Updated “Features” on page 1. Updated Figure 1-1 on page 2 ...
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ATtiny25/45/85 29 ...
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