ATUC128D3 Atmel Corporation, ATUC128D3 Datasheet - Page 108
ATUC128D3
Manufacturer Part Number
ATUC128D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC128D3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- ATUC128D3 PDF datasheet #4
- ATUC128D3 PDF datasheet #5
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9.3.4
Table 9-4.
108
Mnemonics
addhh.w
machh.d
machh.w
macwh.d
mulhh.w
mulwh.d
mulnhh.w
mulnwh.d
satadd.h
satadd.w
satsub.h
satsub.w
satrnds
satrndu
sats
satu
subhh.w
AVR32
DSP Operations
DSP Operations
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Operands / Syntax
Rd, Rx:<part>,
Ry:<part>
Rd, Rx:<part>,
Ry:<part>
Rd, Rx:<part>,
Ry:<part>
Rd, Rx, Ry:<part>
Rd, Rx:<part>,
Ry:<part>
Rd, Rx, Ry:<part>
Rd, Rx:<part>,
Ry:<part>
Rd, Rx, Ry:<part>
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rs, imm
Rd >> sa, bp
Rd >> sa, bp
Rd >> sa, bp
Rd >> sa, bp
Rd, Rx:<part>,
Ry:<part>
Rd, Rx, Ry
Description
Add signed halfwords.
(32 ← 16 +16)
Multiply signed halfwords and
accumulate.
(48 ← 16x16 + 48)
Multiply signed halfwords and
accumulate.
(32 ← 16x16 + 32)
Multiply signed word and halfword and
accumulate.
(48 ← 32x16 + 48)
Signed Multiply of halfwords.
(32 ← 16 x 16)
Unsigned Multiply, word and halfword.
48 ← (32 x 16)
Signed Multiply of halfwords.
(32 ← 16 x 16)
Signed Multiply, word and negated
halfword.
48 ← (32 x 16)
Saturated add halfwords.
Saturated add.
Saturated subtract halfwords.
Saturated subtract.
Signed saturate from bit given by sa5 after
a right shift with rounding of bp5 bit
positions.
Unsigned saturate from bit given by sa5
after a right shift with rounding of bp5 bit
positions.
Signed saturate from bit given by sa5 after
a right shift of bp5 bit positions.
Unsigned saturate from bit given by sa5
after a right shift of bp5 bit positions.
Subtract signed halfwords.
(32 ← 16 -16)
Operation
Rd ← SE(Rx:<part>) +
SE(Ry:<part>)
Rd+1:Rd ← Rx:<part> * Ry:<part>
+ Rd+1:Rd
Rd ← Rx:<part> * Ry:<part> + Rd
Rd+1:Rd ← ((Rx * Ry:<part>)
<<16) + Rd+1:Rd
Rd ← Rx:<part> * Ry:<part>
Rd+1:Rd ← ((Rx * Ry:<part>)
<<16)
Rd ← Rx:<part> * (- Ry:<part>)
Rd+1:Rd ← ((Rx * (- Ry:<part>))
<< 16)
Rd ← SE(Sat(Rx[15:0] +
Ry[15:0]))
Rd ← Sat(Rx + Ry)
Rd ← SE(Sat(Rx[15:0] - Ry[15:0]))
Rd ← Sat(Rx - Ry)
Rd ← Sat(Rs - SE(imm16) )
Rd ← Sat(Round((Rd >> sa5)),
bp5)
Rd ← Sat(Round((Rd >> sa5)),
bp5)
Rd ← Sat((Rd >> sa5), bp5)
Rd ← Sat((Rd >> sa5),bp5)
Rd ← SE(Rx:<part>) -
SE(Ry:<part>)
32000D–04/2011
Rev
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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