ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet
ATUC128L4U
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ATUC128L4U Summary of contents
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... PWM with a Source Clock up to 150MHz • Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independent Baudrate Generator, Support for SPI Interfaces – Support for Hardware Handshaking ® ® AVR Microcontroller 32-bit Atmel AVR Microcontroller ATUC256L3U ATUC128L3U ATUC64L3U ATUC256L4U ATUC128L4U ATUC64L4U 32142A–12/2011 ...
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One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals – SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I • One 8-channel Analog-to-digital Converter (ADCIFB) with up to ...
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Description The Atmel on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 high- performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applica- tions, with particular emphasis on low power consumption, high ...
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The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing known reference clock. The Full-speed USB 2.0 device interface (USBC) supports several USB classes at the same time, thanks to the rich end-point configuration. ...
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Overview 2.1 Block Diagram Figure 2-1. RESET_N PA PB 32142A–12/2011 Block Diagram MCKO MDO[5..0] MSEO[1..0] AVR32UC CPU EVTI_N NEXUS EVTO_N CLASS 2+ TCK MEMORY PROTECTION UNIT JTAG OCD TDO INTERFACE TDI INSTR TMS INTERFACE DATAOUT aWire M M S/M ...
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... Phase Locked Loop 40-240MHz (PLL) Crystal Oscillator 0.45-16MHz (OSC0) Crystal Oscillator 32KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115kHz (RCSYS) RC Oscillator 32kHz (RC32K) 8-channel 12-bit 50MHz TQFP64/QFN64 ATUC64/128/256L3/4U ATUC256L4U ATUC128L4U ATUC64L4U 256KB 128KB 32KB TQFP48/QFN48/TLLGA48 64KB 16KB 6 ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32142A–12/2011 ATUC64/128/256L4U TQFP48/QFN48 Pinout ...
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Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32142A–12/2011 ATUC64/128/256L4U TLLGA48 Pinout ATUC64/128/256L3/4U 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 ...
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Figure 3-3. PA15 PA16 PA17 PA19 PA18 PB23 PB24 PB11 PB15 PB16 PB17 PB18 PB25 PA10 PA12 VDDIO 32142A–12/2011 ATUC64/128/256L3U TQFP64/QFN64 Pinout ATUC64/128/256L3/4U 32 ...
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Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing G ...
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Table 3-1. GPIO Controller Function Multiplexing 39 51 PA17 17 VDDIO 41 53 PA18 18 VDDIO 40 52 PA19 19 VDDIO 25 33 PA20 20 VDDIN 24 32 PA21 21 VDDIN 9 13 PA22 22 VDDIO 6 8 PB00 32 ...
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Table 3-1. GPIO Controller Function Multiplexing 58 PB16 48 VDDIO 59 PB17 49 VDDIO 60 PB18 50 VDDIO 4 PB19 51 VDDIO 5 PB20 52 VDDIO 40 PB21 53 VDDIO 41 PB22 54 VDDIO 54 PB23 55 VDDIO 55 PB24 ...
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Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the ...
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Table 3-4. Pin EVTO_N MCKO MSEO[1] MSEO[0] 3.2.6 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for ...
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Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Descriptions List Signal Name Function CLK D/A Clock out DAC1 - DAC0 D/A Bitstream out DACN1 - DACN0 D/A Inverted bitstream out ACAN3 ...
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Table 3-7. Signal Descriptions List ISCK I2S Serial Clock ISDI I2S Serial Data In ISDO I2S Serial Data Out IWS I2S Word Select TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select RESET_N Reset ...
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Table 3-7. Signal Descriptions List B1 Channel 1 Line B B2 Channel 2 Line B CLK0 Channel 0 External Clock Input CLK1 Channel 1 External Clock Input CLK2 Channel 2 External Clock Input TWALM SMBus SMBALERT TWCK Two-wire Serial Clock ...
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Table 3-8. Signal Description List, Continued Signal Name Function EVTI_N Event In EVTO_N Event Out PA22 - PA00 Parallel I/O Controller I/O Port 0 PB27 - PB00 Parallel I/O Controller I/O Port 1 Note: 1. See Section 6. on page ...
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TWI Pins PA05/PA07/PA17 When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics ...
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ADC Input Pins These pins are regular I/O pins powered from the VDDIO. However, when these pins are used for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot ...
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Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack ...
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Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...
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Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d 4.3.2.5 Unimplemented Instructions ...
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Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...
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Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...
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Table 4-3. Reg # 33- ...
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Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...
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EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...
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Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...
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An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...
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Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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... ATUC128L4U) – 64Kbytes (ATUC64L3U, ATUC64L4U) • Internal high-speed SRAM, single-cycle access at full speed – 32Kbytes (ATUC256L3U, ATUC256L4U, ATUC128L3U, ATUC128L4U) – 16Kbytes (ATUC64L3U, ATUC64L4U) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even during boot ...
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Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE0400 0xFFFE0800 0xFFFE1000 0xFFFF0000 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 32142A–12/2011 Peripheral Name FLASHCDW Flash Controller - FLASHCDW HMATRIX HSB Matrix - ...
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Table 5-3. Peripheral Address Mapping 0xFFFF4400 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 0xFFFF7400 0xFFFF7800 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in ...
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The following GPIO registers are mapped on the local bus: Table 5-4. Port 0 1 32142A–12/2011 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) ...
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Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The ATUC64/128/256L3/4U has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. • VDDIN: Powers I/O lines, the USB pins, and ...
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Regulator Connection The ATUC64/128/256L3/4U supports three power supply configurations: • 3.3V single supply mode – Shutdown mode is not available • 1.8V single supply mode – Shutdown mode is not available • 3.3V supply mode, with 1.8V regulated I/O ...
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Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). ...
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Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8 V supply as shown in same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. ...
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Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in use Shutdown mode. Figure 6-4. 1.98-3.6V ...
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Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise ...
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Peripheral DMA Controller (PDCA) Rev: 1.2.3.1 7.1 Features • Multiple channels • Generates transfers between memories and peripherals such as USART and SPI • Two address pointers/counters per channel allowing double buffering • Performance monitors to measure average and ...
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Block Diagram Figure 7-1. High Speed Bus Matrix Controller 7.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 7.4.1 Power Management If the CPU enters a sleep ...
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Peripheral Events The PDCA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 7.5 Functional Description 7.5.1 Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of ...
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If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the value written in TCRR and MARR. 7.5.5 Ring Buffer When Ring Buffer mode is enabled the TCRR and MARR registers will not be ...
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Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest ...
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The registers can also be manually reset by writing a one to the Channel Reset bit in the PCON- TROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is reached. ...
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User Interface 7.7.1 Memory Map Overview Table 7-1. PDCA Register Memory Map Address Range 0x000 - 0x03F 0x040 - 0x07F ... (0x000 - 0x03F)+m*0x040 0x800-0x830 0x834 The channels are mapped as shown in ters, shown in 7.7.2 Channel Memory ...
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Performance Monitor Memory Map Table 7-3. PDCA Performance Monitor Registers Offset 0x800 Performance Control Register 0x804 Channel0 Read Data Cycles 0x808 Channel0 Read Stall Cycles 0x80C Channel0 Read Max Latency 0x810 Channel0 Write Data Cycles 0x814 Channel0 Write Stall ...
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Memory Address Register Name: MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the ...
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Peripheral Select Register Name: PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral ...
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Transfer Counter Register Name: TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 • TCV: Transfer Counter Value Number of data items to be transferred ...
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Memory Address Reload Register Name: MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will ...
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Transfer Counter Reload Register Name: TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 • TCRV: Transfer Counter Reload Value Reload value for the TCR ...
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Control Register Name: CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 • ECLR: Transfer Error Clear Writing a zero to ...
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Mode Register Name: MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 • RING: Ring Buffer 0:The Ring buffer functionality is ...
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Status Register Name: SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 • TEN: Transfer Enabled This bit is cleared when ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 • TERR: Transfer Error This bit is cleared ...
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Performance Control Register Name: PCONTROL Access Type: Read/Write Offset: 0x800 Reset Value: 0x00000000 • MON1CH: Performance Monitor Channel 1 • MON0CH: Performance Monitor ...
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Performance Channel 0 Read Data Cycles Name: PRDATA0 Access Type: Read-only Offset: 0x804 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Read Stall Cycles Name: PRSTALL0 Access Type: Read-only Offset: 0x808 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Read Max Latency Name: PRLAT0 Access Type: Read/Write Offset: 0x80C Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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Performance Channel 0 Write Data Cycles Name: PWDATA0 Access Type: Read-only Offset: 0x810 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Write Stall Cycles Name: PWSTALL0 Access Type: Read-only Offset: 0x814 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 0 Write Max Latency Name: PWLAT0 Access Type: Read/Write Offset: 0x818 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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Performance Channel 1 Read Data Cycles Name: PRDATA1 Access Type: Read-only Offset: 0x81C Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Read Stall Cycles Name: PRSTALL1 Access Type: Read-only Offset: 0x820 Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Read Max Latency Name: PRLAT1 Access Type: Read/Write Offset: 0x824 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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Performance Channel 1 Write Data Cycles Name: PWDATA1 Access Type: Read-only Offset: 0x828 Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Write Stall Cycles Name: PWSTALL1 Access Type: Read-only Offset: 0x82C Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB ...
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Performance Channel 1 Write Max Latency Name: PWLAT1 Access Type: Read/Write Offset: 0x830 Reset Value: 0x00000000 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock ...
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PDCA Version Register Name: VERSION Access Type: Read-only Offset: 0x834 Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number ...
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Module Configuration The specific configuration for each PDCA instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man- ager chapter for details. Table 7-6. ...
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Table 7-9. PID 32142A–12/2011 Peripheral Identity Values Direction Peripheral Instance RX USART3 ...
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USB Interface (USBC) Rev: 2.0.0.15 8.1 Features • Compatible with the USB 2.0 specification • Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication • Seven physical pipes/endpoints in ping-pong mode • Flexible pipe/endpoint configuration and reallocation of data buffers ...
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User interface • USB Core • Transceiver pads Figure 8-1. HSB PB Interrupt Controller SCIF Note: 32142A–12/2011 USBC Block Diagram USB HSB Master User interface USB interrupts GCLK_USBC @ 48 MHz in the block diagram is symbolic ...
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I/O Lines Description Table 8-2. I/O Lines Description PIn Name Pin Description DM Data -: Differential Data Line - Port DP Data +: Differential Data Line + Port 32142A–12/2011 ATUC64/128/256L3/4U Type Active Level Input/Output Input/Output 83 ...
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Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 8.5.1 I/O Lines The USBC pins may be multiplexed with the I/O Controller lines. The user must first configure ...
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Functional Description 8.6.1 USB General Operation 8.6.1.1 Initialization After a hardware reset, the USBC is in the Reset state. In this state: • The module is disabled. The USBC Enable bit in the General Control register (USBCON.USBE) is reset. ...
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Figure 8-2. 8.6.1.5 Data management Endpoints and pipe buffers can be allocated anywhere in the embedded memory (CPU RAM or HSB RAM). See ”RAM management” on page 8.6.1.6 Pad Suspend Figure 8-3 Figure 8-3. • In Idle state, the pad ...
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Figure 8-4. The Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP) is set and the Wakeup Interrupt (UDINT.WAKEUP) bit is cleared when a USB Suspend state has been detected on the USB bus. This event automatically puts the ...
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USBC Device Mode Operation 8.6.2.1 Device Enabling In device mode, the USBC supports full- and low-speed data transfers. Including the default control endpoint, a total of seven endpoints are provided. They can be con- figured as isochronous, bulk or ...
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After all kinds of resets, the USB device address is 0. • The host starts a SETUP transaction with a SET_ADDRESS(addr) request. • The user writes this address to the USB Address field (UDCON.UADD), and writes a zero to ...
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The user may then write a one to the remote wakeup (RMWKUP) bit in UDCON to send an Upstream Resume to the host initiating the wakeup. This will automatically be done by the controller after 5ms of inactivity on ...
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Figure 8-5. Each descriptor of an endpoint n consists of four words. • The address of the endpoint and the bank used (EPn_ADDR_BK0/1). • The packet size information for the endpoint and bank (EPn_PCKSIZE_BK0/1): Table 8-3. AUTO_ZLP – AUTO_ZLP: Auto ...
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The control and status fields for the endpoint and bank (EPn_CTR_STA_BK0/1): Table 8-4. 31:19 - – UNDERF: Underflow status for isochronous IN transfer. See – OVERF: Overflow status for isochronous OUT transfer. See – CRCERR: CRC error status for ...
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Multi packet mode and single packet mode. Single packet mode is the default mode where one USB packet is managed per bank. The multi-packet mode allows the user to manage data exceeding the maximum endpoint size (UECFGn.EPSIZE) for an ...
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Figure 8-6. SETUP USB Bus SETUP RXSTPI RXOUTI TXINI • Control read Figure 8-7 on page 94 neous write requests from the CPU and USB host. Figure 8-7. SETUP USB Bus SETUP RXSTPI RXOUTI TXINI Wr Enable HOST Wr Enable ...
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Management of IN endpoints • Overview IN packets are sent by the USBC device controller upon IN requests from the host. The endpoint and its descriptor in RAM must be pre configured (see section ment” on page 90 When ...
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Detailed description The data is written according to this sequence: • When the bank is empty, TXINI and FIFOCON are set, which triggers an EPnINT interrupt if TXINE is one. • The user acknowledges the interrupt by clearing TXINI. ...
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EPSIZE, whereby the last packet should be short. To enable the multi packet mode, the user should configure the endpoint descriptor (EPn_PCKSIZE_BK0/1.BYTE_COUNT) to the total size of ...
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Figure 8-12. Example of an OUT endpoint with two data banks DATA OUT (bank 0) RXOUTI FIFOCON • Detailed description Before using the OUT endpoint, one should properly initialize its descriptor for each bank. See Figure 8-5 on page The ...
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A packet has been successfully received and the updated BYTE_COUNT equals the MULTI_PACKET_SIZE. • A short packet (smaller than EPSIZE) has been received. 8.6.2.16 Data flow error This error exists only for isochronous IN/OUT endpoints. It sets the Errorflow ...
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The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one) • Endpoint interrupts The processing device endpoint interrupts are: • The Transmitted IN Data Interrupt (TXINI) • The Received OUT Data Interrupt (RXOUTI) • ...
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User Interface Table 8-5. USBC Register Memory Map Offset 0x0000 Device General Control Register 0x0004 Device Global Interrupt Register 0x0008 Device Global Interrupt Clear Register 0x000C Device Global Interrupt Set Register 0x0010 Device Global Interrupt Enable Register 0x0014 Device ...
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USB General Registers 8.7.1.1 General Control Register Name: USBCON Access Type: Read/Write Offset: 0x0800 Reset Value: 0x00004000 USBE FRZCLK • USBE: USBC Enable Writing a ...
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General Status Register Register Name: USBSTA Access Type: Read-Only Offset: 0x0804 Reset Value: 0x00000000 CLKUSABLE • CLKUSABLE: Generic Clock Usable This bit is cleared ...
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General Status Clear Register Register Name: USBSTACLR Access Type: Write-Only Offset: 0x0808 Reset Value: 0x00000000 Writing a zero to a bit in this ...
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General Status Set Register Register Name: USBSTASET Access Type: Write-Only Offset: 0x080C Reset Value: 0x00000000 Writing a zero to a bit in this ...
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Version Register Register Name: UVERS Access Type: Read-Only Offset: 0x0818 Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number ...
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Features Register Register Name: UFEATURES Access Type: Read-Only Offset: 0x081C Reset Value • EPTNBRMAX: Maximal Number of pipes/endpoints This field indicates the ...
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Address Size Register Register Name: UADDRSIZE Access Type: Read-Only Offset: 0x0820 Reset Value • UADDRSIZE Address Size This field indicates the size of the PB address space reserved ...
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IP Name Register 1 Register Name: UNAME1 Access Type: Read-Only Offset: 0x0824 Reset Value • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name ...
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IP Name Register 2 Register Name: UNAME2 Access Type: Read-Only Offset: 0x0828 Reset Value • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of ...
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Finite State Machine Status Register Register Name: USBFSM Access Type: Read-Only Offset: 0x082C Reset Value: 0x00000009 • DRDSTATE: Dual Role Device State This ...
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USB Descriptor Address Register Name: UDESC Access Type: Read-Write Offset: 0x0830 Reset Value • UDESCA: USB Descriptor Address This field contains the address of the USB descriptor. The three least ...
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USB Device Registers 8.7.2.1 Device General Control Register Register Name: UDCON Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000100 ADDEN • GNAK: Global NAK 0: ...
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Device Global Interrupt Register Register Name: UDINT Access Type: Read-Only Offset: 0x0004 Reset Value: 0x00000000 (1) (1) EP3INT EP2INT EP1INT UPRSM Note: 1. EPnINT bits are ...
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SUSP: Suspend Interrupt This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt or when the Wakeup (WAKEUP) interrupt bit is set. This bit is set when a USB “Suspend” idle bus state ...
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Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Write-Only Offset: 0x0008 Reset Value: 0x00000000 UPRSMC EORSMC Writing a zero to a bit ...
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Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Write-Only Offset: 0x000C Reset Value: 0x00000000 UPRSMS EORSMS Writing a zero to a bit ...
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Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Read-Only Offset: 0x0010 Reset Value: 0x00000000 (1) (1) EP3INTE EP2INTE EP1INTE UPRSME EORSME Note: 1. EPnINTE ...
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Device Global Interrupt Enable Clear Register Register Name: UDINTECLR Access Type: Write-Only Offset: 0x0014 Reset Value: 0x00000000 (1) (1) EP3INTEC EP2INTEC EP1INTEC UPRSMEC EORSMEC Note: 1. ...
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Device Global Interrupt Enable Set Register Register Name: UDINTESET Access Type: Write-Only Offset: 0x0018 Reset Value: 0x00000000 (1) (1) EP3INTES EP2INTES EP1INTES UPRSMES EORSMES Note: 1. ...
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Endpoint Enable/Reset Register Register Name: UERST Access Type: Read/Write Offset: 0x001C Reset Value: 0x00000000 (1) (1) EPEN7 EPEN6 EPEN5 • EPENn: Endpoint n Enable Note: ...
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Device Frame Number Register Register Name: UDFNUM Access Type: Read-Only Offset: 0x0020 Reset Value: 0x00000000 FNCERR - 7 6 FNUM[4:0] • FNCERR: Frame Number CRC Error This bit is ...
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Endpoint n Configuration Register Register Name: UECFGn [0..6] Access Type: Read/Write Offset: 0x0100 + (n * 0x04) Reset Value: 0x00000000 • EPTYPE: ...
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EPSIZE This field is cleared upon receiving a USB reset (except for the endpoint 0). • EPBK: Endpoint Banks This bit selects the number of banks for the endpoint: 0: single-bank ...
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Endpoint n Status Register Register Name: UESTAn [0..6] Access Type: Read-Only 0x0100 Offset: 0x0130 + (n * 0x04) Reset Value: 0x00000000 CURRBK 7 6 STALLEDI/ - CRCERRI ...
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For IN endpoints, this indicates the number of banks filled by the user and ready for IN transfers. When all banks are free an EPnINT interrupt will be triggered if NBUSYBKE is one. For OUT endpoints, this indicates the number ...
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This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPnINT interrupt if RXOUTE is one. This bit is set for isochronous, bulk and, interrupt OUT endpoints, ...
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Endpoint n Status Clear Register Register Name: UESTAnCLR [0..6] Access Type: Write-Only Offset: 0x0160 + (n * 0x04) Reset Value: 0x00000000 STALLEDIC/ - ...
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Endpoint n Status Set Register Register Name: UESTAnSET [0..6] Access Type: Write-Only Offset: 0x0190 + (n * 0x04) Reset Value: 0x00000000 STALLEDIS/ - ...
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Endpoint n Control Register Register Name: UECONn [0..6] Access Type: Read-Only Offset: 0x01C0 + (n * 0x04) Reset Value: 0x00000000 FIFOCON 7 6 STALLEDE/ - CRCERRE ...
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KILLBK: Kill IN Bank This bit is cleared by hardware after the completion of the “kill packet procedure”. This bit is set when the KILLBKS bit is written to one, killing the last written bank. The user shall wait ...
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Endpoint n Control Clear Register Register Name: UECONnCLR [0..6] Access Type: Write-Only Offset: 0x0220 + (n * 0x04) Reset Value: 0x00000000 FIFOCONC 7 6 STALLEDEC/ - ...
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Endpoint n Control Set Register Register Name: UECONnSET [0..6] Access Type: Write-Only Offset: 0x01F0 + (n * 0x04) Reset Value: 0x00000000 KILLBKS 7 6 STALLEDES/ ...
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Module Configuration The specific configuration for each USBC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man- ager chapter for details. Table ...
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Flash Controller (FLASHCDW) Rev: 1.2.0.0 9.1 Features • Controls on-chip flash memory • Supports 0 and 1 wait state bus access • Buffers reducing penalty of wait state in sequential code or loops • Allows interleaved burst reads for ...
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Debug Operation When an external debugger forces the CPU into debug mode, the FLASHCDW continues nor- mal operation. If the FLASHCDW is configured in a way that requires periodically serviced by the CPU through interrupts or ...
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The first word is output on the bus, and the other word is put into an internal buffer read to a sequential address performed ...
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Figure 9-1. 9.4.5 High Speed Read Mode The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the cost of higher power consumption. Two dedicated commands, High Speed Read Mode Enable (HSEN) and High Speed ...
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Figure 9-2. 9.4.6 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result ...
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Figure 9-3. All locations are doubleword locations Internally, the flash memory stores data in 64-bit doublewords. Therefore, the native data size of the Page Buffer is also a 64-bit doubleword. All locations ...
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The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded ...
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After programming, the page can be locked to prevent miscellaneous write or erase sequences. Locking is performed on a per-region basis, so locking a region locks all pages inside the region. Additional protection is provided for the lowermost address space ...
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Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: At least one lock region is protected, or BOOTPROT is different from 0. The erase command has been aborted and ...
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Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions: Table 9-2. General- Purpose fuse number 15:0 16 19:17 21:20 22 The BOOTPROT fuses protects ...
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Table 9-3. BOOTPROT The SECURE fuses have the following functionality: Table 9-5. SECURE erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) ...
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Security Bit The security bit allows the entire device to be locked from external JTAG, aWire, or other debug access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, ...
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User Interface Table 9-6. FLASHCDW Register Memory Map Offset 0x00 Flash Control Register 0x04 Flash Command Register 0x08 Flash Status Register 0x0C Flash Parameter Register 0x10 Flash Version Register 0x14 Flash General Purpose Fuse Register Hi 0x18 Flash General ...
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Flash Control Register Name: FCR Access Type: Read/Write Offset : 0x00 Reset Value: 0x00000000 FWS • BRBUF: Branch Target Instruction Buffer Enable 0: The ...
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Flash Command Register Name: FCMD Access Type: Read/Write Offset : 0x04 Reset Value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write ...
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Table 9-7. Semantic of PAGEN field in different commands Command Program GP Fuse Byte Erase All GP Fuses Quick Page Read Write User Page Erase User Page Quick Page Read User Page High Speed Mode Enable High Speed Mode Disable ...
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Flash Status Register Name: FSR Access Type: Read-only Offset : 0x08 Reset Value: 0x00000000 31 30 LOCK15 LOCK14 23 22 LOCK7 LOCK6 HSMODE • LOCKx: Lock Region x Lock Status 0: The ...
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Flash Parameter Register Name: FPR Access Type: Read-only Offset : 0x0C Reset Value • PSZ: Page Size The size of each flash ...
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FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 9-10. Flash Size FSZ Flash Size FSZ 0 4 Kbyte Kbyte ...
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Flash Version Register Name: FVR Access Type: Read-only Offset : 0x10 Reset Value: 0x00000000 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version ...
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Flash General Purpose Fuse Register High Name: FGPFRHI Access Type: Read-only Offset : 0x14 Reset Value GPF63 GPF62 23 22 GPF55 GPF54 15 14 GPF47 GPF46 7 6 GPF39 GPF38 This register is only used in ...
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Flash General Purpose Fuse Register Low Name: FGPFRLO Access Type: Read-only Offset : 0x18 Reset Value GPF31 GPF30 23 22 GPF23 GPF22 15 14 GPF15 GPF14 7 6 GPF07 GPF06 • GPFxx: General Purpose Fuse xx ...
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Fuse Settings The flash contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO). The Flash General Purpose Fuse Register High (FGPFRHI) is not used. In addition to the ...
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Flash General Purpose Fuse Register Low (FGPFRLO BODEN 23 22 BODLEVEL[0] UPROT • BODEN: Brown Out Detector Enable BODEN Description 00 BOD disabled 01 BOD enabled, BOD reset enabled 10 BOD enabled, BOD ...
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First Word of the User Page (Address 0x80800000 • WDTAUTO: WatchDog Timer Auto Enable at Startup 0: The WDT is automatically enabled at ...
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... FLASHCDW 32142A–12/2011 SSADRR[15: SSADRR[7: SSADRF[15: SSADRF[7:0] Module Configuration ATUC256L3U, ATUC128L3U, ATUC256L4U ATUC128L4U 256Kbytes 128Kbytes 512 256 512 bytes 512 bytes Module Clock Name Clock Name CLK_FLASHCDW_HSB CLK_FLASHCDW_PB ATUC64/128/256L3/ ATUC64L3U, ATUC64L4U 64Kbytes ...
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... Table 9-13. Register FVR FPR 32142A–12/2011 Register Reset Values ATUC256L3U, ATUC256L4U 0x00000120 0x00000409 ATUC64/128/256L3/4U ATUC128L3U, ATUC64L3U, ATUC128L4U ATUC64L4U 0x00000120 0x00000120 0x00000407 0x00000405 161 ...
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Secure Access Unit (SAU) Rev: 1.1.1.3 10.1 Features • Remaps registers in memory regions protected by the MPU to regions not protected by the MPU • Programmable physical address for each channel • Two modes of operation: Locked and ...
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Block Diagram Figure 10-1 some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB) and the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory accesses are ...
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Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 10.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the SAU, the SAU ...
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Protecting SAU configuration registers In order to prevent the SAU configuration registers to be changed by malicious or runaway code, they should be protected by the MPU as soon as they have been configured. Maximum security is provided in ...
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Operation example Figure 10-2 als, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has ...
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Unlock Register Error Status (URES) is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits in SR were set (see 10.5.6). The unlock operation was aborted. ...
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User Interface The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base address. Table 10-1. SAU Configuration Register Memory Map Offset 0x00 0x04 0x08 Channel Enable Register High 0x0C Channel ...
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Control Register Name: CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 BERRDIS • BERRDIS: Bus Error Response Disable Writing a zero to ...
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Configuration Register Name: CONFIG Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 • OPEN: Open Mode Enable Writing a zero to this bit disables open mode. Writing ...
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Channel Enable Register High Name: CERH Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • CERH[n]: Channel Enable Register High 0: Channel (n+32) is not enabled. 1: Channel (n+32) is ...
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Channel Enable Register Low Name: CERL Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 • CERL[n]: Channel Enable Register Low 0: Channel n is not enabled. 1: Channel n is enabled. ...
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Status Register Name: SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000400 RTRADR MBERROR • IDLE This bit is cleared when a read or write ...
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CAU: Channel Access Unsuccessful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access was unsuccessful, i.e. an access was attempted to a locked or disabled channel. • ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 RTRADR MBERROR 0: The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 RTRADR MBERROR Writing a zero to a bit in this register has ...
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Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x24 Reset Value • CHANNELS: Number of channels implemented. 32142A–12/2011 ...
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Version Register Name: VERSION Access Type: Write-only Offset: 0x28 Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version ...
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Remap Target Register n Name: RTRn Access Type: Read/Write Offset: n*4 Reset Value: 0x00000000 • RTR: Remap Target Address for Channel n RTR[31:16] must have one of the following values, any ...
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Unlock Register Name: UR Access Type : Write-only Offset: 0xFC Reset Value: 0x00000000 • KEY: Unlock Key The correct key must be written in order ...
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Module Configuration The specific configuration for each SAU instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 10-3. Feature ...
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HSB Bus Matrix (HMATRIXB) Rev: 1.3.0.3 11.1 Features • User Interface on peripheral bus • Configurable number of masters (up to 16) • Configurable number of slaves (up to 16) • One decoder for each master • Programmable arbitration ...
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To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE ...
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Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix pro- vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst ...
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Other non privileged masters still get one latency cycle if they want to access the same slave. This technique ...
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User Interface Table 11-1. HMATRIX Register Memory Map Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration Register ...
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Table 11-1. HMATRIX Register Memory Map (Continued) Offset Register 0x008C Priority Register B for Slave 1 0x0090 Priority Register A for Slave 2 0x0094 Priority Register B for Slave 2 0x0098 Priority Register A for Slave 3 0x009C Priority Register ...
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Table 11-1. HMATRIX Register Memory Map (Continued) Offset Register 0x012C Special Function Register 7 0x0130 Special Function Register 8 0x0134 Special Function Register 9 0x0138 Special Function Register 10 0x013C Special Function Register 11 0x0140 Special Function Register 12 0x0144 ...
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Master Configuration Registers Name: MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 – – – – – – – – • ULBT: Undefined Length Burst Type Table 11-2. ...
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Slave Configuration Registers Name: SCFG0...SCFG15 Access Type: Read/Write Offset: 0x40 - 0x7C Reset Value: 0x00000010 31 30 – – – – – – • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority ...
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Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 • MxPR: Master x Priority ...
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Priority Registers B For Slaves Name: PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 • MxPR: Master x Priority Fixed priority of ...
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Special Function Registers Name: SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x14C Reset Value • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field ...
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Module Configuration The specific configuration for each HMATRIX instance is listed in the following tables.The mod- ule bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 11-3. ...
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Figure 11-1. HMatrix Master / Slave Connections 32142A–12/2011 ATUC64/128/256L3/4U HMATRIX SLAVES 0 1 CPU Data 0 CPU 1 Instruction CPU SAB 2 SAU 3 PDCA 4 USBC 197 ...
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Interrupt Controller (INTC) Rev: 1.0.2.5 12.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • groups of interrupts with ...
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Figure 12-1. INTC Block Diagram NMIREQ IREQ63 IREQ34 IREQ33 IREQ32 IREQ31 IREQ2 IREQ1 IREQ0 12.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 12.4.1 Power Management If the ...
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Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, ...