ATxmega256D3 Atmel Corporation, ATxmega256D3 Datasheet - Page 53

• Manufacturer Part Number: ATxmega256D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256D3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8134I–AVR–12/10
Mnemonics
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
MOV
MOVW
LDI
LDS
LD
LD
LD
LD
LD
Operands
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rr, b
Rr, b
A, b
A, b
s, k
s, k
Rd, Rr
Rd, Rr
Rd, K
Rd, k
Rd, X
Rd, X+
Rd, -X
Rd, Y
Rd, Y+
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Description
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Copy Register
Copy Register Pair
Load Immediate
Load Direct from data space
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Data Transfer Instructions
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (N ⊕ V= 0) then PC
if (N ⊕ V= 1) then PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (C = 0) then PC
if (N = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (Rd = Rr) PC
Rd - Rr - C
X ← X - 1,
Rd ← (X)
Rd ← (Y)
Rd+1:Rd
Rd - Rr
Rd - K
Operation
PC
PC
Rd
Rd
Rd
Rd
Rd
Rd
X
Y
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
STACK
STACK
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
Rr
Rr+1:Rr
K
(k)
(X)
(X)
X + 1
X - 1
(X)
(Y)
(Y)
Y + 1
XMEGA D3
Flags
None
I
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clocks
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
4 / 5
4 / 5
2
1
1
2
1
1
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
1
1
1
1
1
1
(1)
(1)
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