ATxmega64B1 Atmel Corporation, ATxmega64B1 Datasheet - Page 206
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ATxmega64B1
Manufacturer Part Number
ATxmega64B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64B1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64B1-AUR
Manufacturer:
ATMEL
Quantity:
210
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17.3.4
17.3.5
17.3.6
8291A–AVR–10/11
INTFLAGS - Interrupt Flag register
TEMP – Temporary Register
CNTL – Counter Register Low
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – COMPIF: Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. It is cleared automati-
cally when the RTC compare match interrupt vector is executed. The flag can also be cleared by
writing a one to its bit location.
• Bit 0 – OVFIF: Overflow Interrupt Flag
This flag is set on the next count after an overflow condition occurs. It is cleared automatically
when the RTC overflow interrupt vector is executed. The flag can also be cleared by writing a
one to its bit location.
• Bit 7:0 – TEMP[7:0]: Real-Time Counter Temporary Register
This register is used for 16-bit access to the counter value, compare value, and TOP value reg-
isters. The low byte of the 16-bit register is stored here when it is written by the CPU. The high
byte of the 16-bit register is stored when the low byte is read by the CPU. For more details, refer
to
The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT counts positive clock
edges on the prescaled RTC clock. Reading and writing 16-bit values requires special attention.
Refer to
Due to synchronization between the RTC clock and system clock domains, there is a latency of
two RTC clock cycles from updating the register until this has an effect. Application software
needs to check that the SYNCBUSY flag in the
cleared before writing to this register.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
”Accessing 16-bit Registers” on page
”Accessing 16-bit Registers” on page 12
R/W
R/W
R
7
–
0
7
0
7
0
R/W
R/W
R
6
–
0
6
0
6
0
R/W
R/W
R
5
–
0
5
0
5
0
12.
R/W
R/W
R
4
–
0
4
0
4
0
TEMP[7:0]
CNT[7:0]
for details.
”STATUS – Status register” on page 205
R/W
R/W
3
–
R
0
3
0
3
0
Atmel AVR XMEGA B
R/W
R/W
2
–
R
0
2
0
2
0
COMPIF
R/W
R/W
R/W
1
0
1
0
1
0
OVFIF
R/W
R/W
R/W
0
0
0
0
0
0
INTFLAGS
TEMP
CNTL
206
is
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