ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet
ATxmega64B3
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ATxmega64B3 Summary of contents
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... TQFP – pad QFN • Operating Voltage – 1.6 – 3.6V • Operating frequency – 0 – 12MHz from 1.6V – 0 – 32MHz from 2.7V ® ® ® AVR XMEGA 8/16-bit Microcontroller 2 C and SMBus compatible) 8/16-bit Atmel XMEGA B3 Microcontroller ATxmega128B3 ATxmega64B3 Preliminary 8074A–AVR–10/11 ...
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... ATxmega128B3-AU 128K + 8K ATxmega64B3-AU 64K + 4K ATxmega128B3-MH 128K + 8K ATxmega64B3-MH 64K + 4K Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. ...
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Pinout/Block Diagram Figure 2-1. Block diagram and pinout PC0 1 PC1 2 PC2 3 PC3 4 PC4 5 PC5 6 PC6 7 PC7 8 GND 9 VCC 10 PD0 11 PD1 12 PDI / RESET 13 PDI 14 GND ...
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Overview The Atmel peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the Atmel AVR XMEGA B3 device achieves throughputs CPU approaching one million instructions per second (MIPS) per ...
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RISC CPU with in-system, self-programmable flash, the Atmel XMEGA pow- erful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. The atmel AVR XMEGA B3 devices are supported with ...
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Block Diagram Figure 3-1. XMEGA B3 Block Diagram VCC/10 Int. Refs. Tempref AREFB ADCB ACB PB[0..7] / PORT B (8) JTAG 8074A–AVR–10/11 PR[0..1] XTAL1 / TOSC1 XTAL2 / TOSC2 Oscillator PORT R (2) Circuits/ Clock Generation EVENT ROUTING NETWORK ...
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA • XMEGA Application Notes This device data sheet only contains part specific information with a short description ...
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AVR CPU 6.1 Features • 8/16-bit, high-performance Atmel AVR RISC CPU – 142 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack pointer accessible in I/O memory space • Direct ...
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information ...
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Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: •Multiplication of unsigned integers •Multiplication of signed integers •Multiplication ...
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During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, ...
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Memories 7.1 Features • Flash program memory – One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage – Boot ...
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Flash Program Memory The Atmel for program storage. The flash memory can be accessed for read and write from an external pro- grammer through the PDI or from application software running in the device. All AVR CPU instructions are ...
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... The device ID for the available devices is shown in The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. ATxmega64B3 ATxmega128B3 7.3.5 User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers ...
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... Data Memory Map (Hexadecimal address) ATxmega128B3 Byte Address 0 I/O Registers (4K) FFF 1000 EEPROM (2K) 17FF RESERVED 2000 Internal SRAM (8K) 3FFF 61. XMEGA B3 ATxmega64B3 0 I/O Registers (4K) FFF 1000 EEPROM (2K) 17FF RESERVED 2000 Internal SRAM (4K) 2FFF ”Periph- 15 ...
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... The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Devices EEPROM Size ATxmega64B3 2K ATxmega128B3 2K 8074A–AVR–10/11 shows the Flash Program Memory organization. Flash write and erase Number of words and pages in the flash ...
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DMAC – Direct Memory Access Controller 8.1 Features • Allows high speed data transfers with minimal CPU intervention – from data memory to data memory – from data memory to peripheral – from peripheral to data memory – from ...
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Event System 9.1 Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events – CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed ...
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Figure 9-1. The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum routing latency is ...
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System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: – 32MHz run-time calibrated oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) ...
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Figure 10-1. The Clock system, clock sources and clock distribution. Brown-out Detector 10.3 Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and ...
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Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy.The oscillator employs a ...
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PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-selectable multiplication factor of from 1 to 31. In combination with the pres- calers, this ...
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Power Management and Sleep Modes 11.1 Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable ...
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Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are ...
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System Control and Reset 12.1 Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset ...
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Reset Sources 12.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V CC sequence. The POR is also activated to power down the device properly when the V ...
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WDT – Watchdog Timer 13.1 Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronous operation from dedicated oscillator • 1kHz output of the 32kHz ultra low power oscillator • 11 ...
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Interrupts and Programmable Multilevel Interrupt Controller 14.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable multilevel interrupt controller – Interrupt prioritizing according to level and vector address ...
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Table 14-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x014 RTC_INT_base 0x018 TWIC_INT_base 0x01C TCC0_INT_base 0x028 TCC1_INT_base 0x030 SPIC_INT_vect 0x032 USARTC0_INT_base 0x03E USB_INT_base 0x046 LCD_INT_base 0x048 AES_INT_vect 0x04A NVM_INT_base 0x04E PORTB_INT_base 0x052 ACB_INT_base 0x058 ADCB_INT_base 0x060 PORTD_INT_base ...
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I/O Ports 15.1 Features • 36 General purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O • Input with synchronous ...
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Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole ...
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Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - ...
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Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7. Input sensing system overview INVERTED I/O When a pin is configured with inverted I/O, the ...
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T/C – 16-bit Timer/Counter Type 0 and 1 16.1 Features • Two 16-bit timer/counters – One timer/counter of type 0 – One timer/counter of type 1 • 32-bit Timer/Counter support by cascading two timer/counters • four compare ...
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A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trig- ger or to synchronize operations. There are two ...
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TC2 –16-bit Timer/Counter Type 2 17.1 Features • A system of two eight-bit timer/counters – Low-byte timer/counter – High-byte timer/counter • Eight compare channels – Four compare channels for the low-byte timer/counter – Four compare channels for the high-byte ...
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AWeX – Advanced Waveform Extension 18.1 Features • Waveform output with complementary output from each compare channel • Four dead-time insertion (DTI) units – 8-bit resolution – Separate high and low side dead-time setting – Double buffered dead time ...
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Hi-Res – High Resolution Extension 19.1 Features • Increases waveform generator resolution bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 19.2 ...
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RTC – 16-bit Real-Time Counter 20.1 Features • 16-bit resolution • Selectable clock source – 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator • Programmable 10-bit clock prescaling • One compare register ...
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USB – Universal Serial Bus Interface 21.1 Features • One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility ...
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The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place. To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, ...
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TWI – Two Wire Interface 22.1 Features • One two-wire interface peripheral • Bidirectional, two-wire communication interface – Phillips I – System Management Bus (SMBus) compatible • Bus master and slave operation supported – Slave operation – Single bus ...
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It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different V PORTC ...
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SPI – Serial Peripheral Interface 23.1 Features • One SPI peripheral • Full-duplex, three-wire synchronous data transfer • Master or slave operation • Lsb first or msb first data transfer • Eight programmable bit rates • Interrupt flag at ...
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USART 24.1 Features • One USART peripheral • Full-duplex operation • Asynchronous or synchronous operation – Synchronous clock rates up to 1/2 of the device clock frequency – Asynchronous clock rates up to 1/8 of the device clock frequency ...
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IRCOM – IR Communication Module 25.1 Features • Pulse modulation/demodulation for infrared communication • IrDA compatible for baud rates up to 115.2kbps • Selectable pulse modulation scheme – 3/16 of the baud rate period – Fixed pulse period, 8-bit ...
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AES and DES Crypto Engine 26.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) crypto module • DES Instruction – Encryption and decryption – DES supported – Encryption/decryption in 16 CPU clock cycles per ...
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CRC – Cyclic Redundancy Check Generator 27.1 Features • Cyclic redundancy check (CRC) generation and checking for – Communication data – Program or data in flash memory – Data in SRAM and I/O memory space • Integrated with flash ...
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LCD - Liquid Crystal Display Controller 28.1 Features • Display capacity segments and common terminals • Supports GPIO's • Shadow display memory gives full freedom in segment update • ASCII ...
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ADC – 12-bit Analog to Digital Converter 29.1 Features • One Analog to Digital Converter (ADC) • 12-bit resolution • 300 thousand samples per second – Down to 2.3µs conversion time with 8-bit resolution – Down to ...
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Figure 29-1. ADC overview ADC0 • • • ADC15 Internal signals ADC0 • • • ADC7 Internal 1.00V Internal VCC/1.6V Internal VCC/2 The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop- agation delay) ...
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AC – Analog Comparator 30.1 Features • Two Analog Comparators (AC) • Selectable hysteresis – No – Small – Large • Analog comparator output available on pin • Flexible input selection – All pins on the port – Bandgap ...
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Figure 30-1. Analog comparator overview Pin Input Pin Input Voltage Scaler Bandgap Pin Input Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 30-2. Analog ...
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Programming and Debugging 31.1 Features • Programming – External programming through PDI or JTAG interfaces – Boot loader support for programming through any communication interface • Debugging – Nonintrusive, real-time, on-chip debug system – No software or hardware resources ...
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Pinout and Pin Functions The device pinout is shown in I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions ...
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Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK D- D+ 32.1.7 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT RTCOUT 32.1.8 Debug/System functions RESET PDI_CLK PDI_DATA TCK TDI TDO TMS 8074A–AVR–10/11 Serial ...
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Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head ...
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Table 32-4. Program and Debug functions PROG PIN # INTERRUPT PDI 13 RESET 14 Table 32-5. LCD (1)(2) (1) LCD PIN # INTERRUPT GND 15 VCC 16 SEG24 17 SYNC SEG23 18 SYNC SEG22 19 SYNC/ASYNC SEG21 20 SYNC SEG20 ...
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Table 32-5. LCD (Continued) (1)(2) (1) LCD PIN # INTERRUPT COM1 50 COM2 51 COM3 52 Notes: 1. Pin mapping of all Segment terminals (SEGn) can be optionnaly swapped. Interrupt, GPIO and Blink functions will be auto- matically swapped. 2. ...
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Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA B3. For complete register description and summary for each peripheral module, refer to the XMEGA B Manual. Base Address 0x0000 0x0010 ...
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Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...
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Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...
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Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...
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Mnemonics Operands Description LAT Z, Rd Load and Toggle RAM location LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd ...
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Packaging information 35.1 64A PIN 0°~7° Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 ...
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D Marked Pin TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA ...
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Electrical Characteristics All typical values are measured 25°C unless other temperature condition is given. All min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 36.1 Absolute Maximum Ratings ...
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The maximum System clock frequency of the Atmel shown in CC 1.8V < V Figure 36-1. Maximum Frequency vs. Vcc 8074A–AVR–10/11 Figure 36-1 on page 69 < 2.7V. CC MHz 32 Safe Operating Area 12 1.6 1.8 ...
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DC Characteristics Table 36-4. Current Consumption for Active and sleep modes Symbol Parameter Condition 32kHz, Ext. Clk 1MHz, Ext. Clk Active Power (1) consumption 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk 1MHz, Ext. Clk Idle Power (1) ...
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Table 36-4. Current Consumption for Active and sleep modes (Continued) Symbol Parameter Condition RTC on ULP clock, WDT, sampled BOD and LCD enabled, and all pixels ON 25°C RTC on 1.024kHz low power 32.768kHz TOSC, LCD enabled and ...
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Table 36-5. Current Consumption for modules and peripherals (Continued) Symbol Parameter Condition No pixel load (2) LCD 22pF - pixel load I CC Internal 1.0V reference Temperature sensor 16kSPS ADC VREF = Ext ref AC DMA 615Kbps between I/O registers ...
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Wake-up time from sleep modes Table 36-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from Idle, Standby, and Extend Standby t wakeup Wake-up time from Power-save and Power-down mode Note: 1. ...
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I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-7. I/O Pin Characteristics Symbol Parameter (1) I ...
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Liquid Crystal Display Characteristics Table 36-8. Liquid Crystal Display Characteristics Symbol Parameter SEG Segment terminal pins COM Common terminal pins f LCD frame frequency Frame C Flying capacitor Flying Contrast Contrast adjustement V LCD BIAS2 LCD regulated voltages BIAS1 ...
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Table 36-10. Clock and timing. (Continued) Symbol Parameter f Sample rate ADC Sampling Time Conversion time (latency) Start-up time ADC settling time Table 36-11. Accuracy characteristics. Symbol Parameter RES Resolution RES Resolution RES Resolution (1) INL Integral non-linearity (1) DNL ...
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Table 36-11. Accuracy characteristics. (Continued) Symbol Parameter Gain Error Gain Error Noise Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, ...
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Analog Comparator Characteristics Table 36-13. Analog Comparator characteristics. Symbol Parameter V Input Offset Voltage off I Input Leakage Current lk Input voltage range AC startup time V Hysteresis, None hys1 V Hysteresis, Small hys2 V Hysteresis, Large hys3 t ...
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Brownout Detection Characteristics Table 36-15. Brownout Detection Characteristics Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling ...
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Flash and EEPROM Memory Characteristics Table 36-18. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 36-19. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not ...
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Calibrated 2MHz RC Internal Oscillator characteristics Table 36-21. Calibrated 2MHz Internal Oscillator characteristics Symbol Parameter Frequency range Factory calibrated frequency Factory calibration accuracy User calibration accuracy DFLL calibration stepsize 36.14.3 Calibrated and tunable 32MHz Internal Oscillator characteristics Table 36-22. ...
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External Clock Characteristics Figure 36-3. External Clock Drive Waveform Table 36-25. External Clock used as System Clock without prescaling Symbol Parameter (1) 1/t Clock Frequency CK t Clock Period CK t Clock High Time CH t Clock Low Time ...
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Table 36-26. External Clock with prescaler Symbol Parameter (2) 1/t Clock Frequency CK t Clock Period CK t Clock High Time CH t Clock Low Time CL t Rise Time (for maximum frequency Fall Time (for maximum frequency) ...
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Symbol Parameter (1) Negative impedance R Q Parasitic capacitance C XTAL1 Parasitic capacitance C XTAL2 Parasitic capacitance load C LOAD Note: 1. Numbers for negative impedance are not tested but guaranteed from design and characterization. 8074A–AVR–10/11 Condition 0.4MHz resonator, CL=100pF ...
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External 32.768kHz crystal oscillator and TOSC characteristics Table 36-28. External 32.768kHz crystal oscillator and TOSC characteristics Symbol Parameter Recommended crystal equivalent ESR/R1 series resistance (ESR) C Input capacitance between TOSC pins IN_TOSC Recommended Safety factor Long term Jitter (SIT) ...
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SPI characteristics Figure 36-5. SPI interface requirements in master mode (CPOL = 0) (CPOL = 1) (Data Input) (Data Output) Figure 36-6. SPI timing requirements in slave mode (CPOL = 0) (CPOL = 1) (Data Input) (Data Output) 8074A–AVR–10/11 ...
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Table 36-29. SPI Timing characteristics and requirements Symbol Parameter t SCK Period SCK t SCK high/low width SCKW t SCK Rise time SCKR t SCK Fall time SCKF t MISO setup to SCK MIS t MISO hold after SCK MIH ...
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Two-Wire Interface Characteristics Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7. Two-Wire Interface Bus ...
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Table 36-30. Two Wire Serial Bus Characteristics (Continued) Symbol Parameter t Data hold time HD;DAT t Data setup time SU;DAT t Setup time for STOP condition SU;STO Bus free time between a STOP and START t BUF condition Notes: 1. ...
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Typical Characteristics 37.1 Active Supply Current TBD 8074A–AVR–10/11 XMEGA B3 90 ...
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Idle Supply Current TBD 8074A–AVR–10/11 XMEGA B3 91 ...
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Power-down Supply Current TBD 37.4 Pin Pull-up Figure 37-1. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage Figure 37-2. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage 140 120 100 ...
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Figure 37-3. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage 160 140 120 100 37.5 Pin Output Voltage vs. Sink/Source Current Figure 37-4. I/O Pin Output Voltage vs. Source Current 1.8 1.6 1.4 1.2 ...
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Figure 37-5. I/O Pin Output Voltage vs. Source Current 2.5 1.5 0.5 Figure 37-6. I/O Pin Output Voltage vs. Source Current 3.5 2.5 1.5 0.5 8074A–AVR–10/11 VOH 25°C, Vcc = -20 -18 -16 ...
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Figure 37-7. I/O Pin Output Voltage vs. Sink Current 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Figure 37-8. I/O Pin Output Voltage vs. Sink Current 0.6 0.5 0.4 0.3 0.2 0.1 0 8074A–AVR–10/11 VIL ...
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Figure 37-9. I/O Pin Output Voltage vs. Sink Current 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 37.6 Pin Thresholds and Hysteresis TBD 8074A–AVR–10/11 VIL 25°C, Vcc = 3. XMEGA ...
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Bod Characteristics Figure 37-10. BOD Thresholds vs. Temperature 3.18 3.16 3.14 3.12 3.08 3.06 3.04 3.02 8074A–AVR–10/11 BOD Level = 7 3.1 3 -40 XMEGA B3 Falling Vcc Rising Vcc 25 85 Temperature (°C) 97 ...
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Oscillators 37.8.1 32.768kHz internal oscillator Figure 37-11. 32.768kHz internal oscillator frequency vs. Temperature 32.8 32.75 32.7 32.65 32.6 32.55 32.5 32.45 32.4 32.35 32.3 Figure 37-12. 32.768kHz internal oscillator frequency vs. Calibration ...
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Figure 37-13. 32.768kHz internal oscillator frequency vs. Calibration 37.8.2 2MHz internal oscillator Figure 37-14. 2MHz internal oscillator frequency vs. Temperature 2.18 2.16 2.14 2.12 2.1 2.08 2.06 2.04 2.02 ...
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Figure 37-15. 2MHz internal oscillator frequency vs. Temperature 1.995 1.99 1.985 1.98 1.975 1.97 37.8.3 32MHZ internal oscillator Figure 37-16. Internal 32MHz oscillator frequency vs. Temperature 36.5 36 35.5 35 34.5 34 33.5 33 32.5 32 31.5 8074A–AVR–10/11 DFLL enabled, ...
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Figure 37-17. 32MHz internal oscillator frequency vs. Temperature 32 31.95 31.9 31.85 31.8 31.75 31.7 31.65 31.6 31.55 31.5 8074A–AVR–10/11 DFLL enabled, from 32.768kHz internal oscillator -40 -30 -20 - XMEGA ...
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LCD Characteristics Figure 37-18. I Figure 37-19. I 8074A–AVR–10/11 vs. Frame Rate CC 32Hz Low P ower Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load ...
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Figure 37-20. I Figure 37-21. I 7.5 6.5 5.5 4.5 3.5 8074A–AVR–10/11 vs. Frame Rate CC 0pF load vs. Contrast CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o ...
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Figure 37-22. I 7.5 7 6.5 6 5.5 5 4.5 4 3.5 3 8074A–AVR–10/11 vs. Contrast CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, V -32 -23 -14 XMEGA ...
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ADC Characteristics Figure 37-23. ADC INL vs. V 1.8 1.6 1.4 1.2 0.8 Figure 37-24. ADC INL vs. V 2.8 2.6 2.4 2.2 1.8 1.6 1.4 1.2 0.8 8074A–AVR–10/11 . REF Differential signed mode 3.6V, external reference ...
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Figure 37-25. ADC DNL vs. V 2.1 1.9 1.7 1.5 1.3 1.1 0.9 Figure 37-26. ADC DNL vs. V 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 8074A–AVR–10/11 . REF Differential signed mode 3.6V, external reference ...
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Figure 37-27. ADC Offset vs Figure 37-28. ADC Offset vs 8074A–AVR–10/ Unsigned mode, ...
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Figure 37-29. ADC Offset vs. V 7.7 7.2 6.7 6.2 5.7 5.2 4.7 4.2 Figure 37-30. ADC Offset vs -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 8074A–AVR–10/11 . REF Differential signed mode 3.6V, ...
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Figure 37-31. ADC Gain Error vs. V -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 -11.0 -12.0 Figure 37-32. ADC Gain Error vs. V -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 8074A–AVR–10/11 . REF Differential signed mode, external ...
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Figure 37-33. ADC Gain Error vs. V -3.2 -3.7 -4.2 -4.7 -5.2 -5.7 -6.2 -6.7 -7.2 Figure 37-34. ADC Gain Error vs. V -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 8074A–AVR–10/ Differential signed ...
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Figure 37-35. ADC Gain Error vs. Temperature. -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 -11.0 -12.0 Figure 37-36. ADC Gain Error vs. Temperature. -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 -9.0 8074A–AVR–10/11 Differential signed mode, external reference -40 -30 -20 -10 0 ...
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Analog comparator characteristics Figure 37-37. Analog comparator propagation delay vs. Vcc Figure 37-38. Analog comparator propagation delay vs. Temperature ...
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PDI characteristics Figure 37-39. Maximum PDI speed vs. Vcc 8074A–AVR–10/11 32 29.5 27 24.5 22 19.5 17 14.5 12 1.6 1.85 2.1 2.35 XMEGA B3 2.6 2.85 3.1 3.35 V [V] CC 25°C -40°C 85°C 3.6 113 ...
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... Errata 38.1 ATxmega64B3, ATxmega128B3 38.1.1 Rev. C • JTAG Revision 1. JTAG Revision is unchanged between Rev. B and Rev. C • AWeX fault protection restore is not done correct in Pattern Generation Mode 1. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 8074A – 10/11 1. 8074A–AVR–10/11 Initial revision. XMEGA ...
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Features ..................................................................................................... 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 4 4 Resources ................................................................................................. 7 5 Capacitive touch sensing ........................................................................ 7 6 AVR CPU ................................................................................................... 8 7 Memories ................................................................................................ 12 8 DMAC – Direct ...
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Event System ......................................................................................... 18 10 System Clock and Clock options ......................................................... 20 11 Power Management and Sleep Modes ................................................. 24 12 System Control and Reset .................................................................... 26 13 WDT – Watchdog Timer ......................................................................... 28 14 Interrupts and Programmable Multilevel ...
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TC2 –16-bit Timer/Counter Type 2 ........................................................ 37 18 AWeX – Advanced Waveform Extension ............................................. 38 19 Hi-Res – High Resolution Extension .................................................... 39 20 RTC – 16-bit Real-Time Counter ........................................................... 40 21 USB – Universal Serial Bus Interface ................................................... ...
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LCD - Liquid Crystal Display Controller .............................................. 50 29 ADC – 12-bit Analog to Digital Converter ............................................ – Analog Comparator ...................................................................... 53 31 Programming and Debugging .............................................................. 55 32 Pinout and Pin Functions ...................................................................... 56 33 ...
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... Supply Current TBD .......................................................................................91 37.3Power-down Supply Current TBD .........................................................................92 37.4Pin Pull-up .............................................................................................................92 37.5Pin Output Voltage vs. Sink/Source Current .........................................................93 37.6Pin Thresholds and Hysteresis TBD ......................................................................96 37.7Bod Characteristics ...............................................................................................97 37.8Oscillators ..............................................................................................................98 37.9LCD Characteristics ............................................................................................102 37.10ADC Characteristics ..........................................................................................105 37.11Analog comparator characteristics ....................................................................112 37.12PDI characteristics ............................................................................................113 38.1ATxmega64B3, ATxmega128B3 .........................................................................114 39.18074A – 10/11 .....................................................................................................115 XMEGA B3 v ...
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... Atmel , Atmel logo and combinations thereof, AVR marks of Atmel Corporation or its subsidiaries. Windows other countries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL ...