M42800A Atmel Corporation, M42800A Datasheet - Page 101

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Receiver
Asynchronous Receiver
Figure 38. Asynchronous Mode: Start Bit Detection
Figure 39. Asynchronous Mode: Character Reception
1354D–ATARM–08/02
Rate Clock
16 x Baud
Sampling
Example: 8-bit, parity enabled 1 stop
Sampling
RXD
RXD
periods
0.5 bit
True Start Detection
The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of
US_MR). In Asynchronous Mode, the USART detects the start of a received character
by sampling the RXD signal until it detects a valid start bit. A low level (space) on RXD is
interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling
clock, which is 16 times the baud rate. Hence a space which is longer than 7/16 of the
bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter
is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the RXD at the theoreti-
cal mid-point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock
(one bit period) so the sampling point is 8 cycles (0.5 bit periods) after the start of the bit.
The first sampling point is therefore 24 cycles (1.5 bit periods) after the falling edge of
the start bit was detected. Each subsequent bit is sampled 16 cycles (1 bit period) after
the previous one.
period
1 bit
D0
D1
True Start
Detection
D2
D3
D4
D5
D6
D7
Parity Bit
AT91X40 Series
Stop Bit
D0
101