R40008 Atmel Corporation, R40008 Datasheet - Page 8

• Manufacturer Part Number: R40008
• Manufacturer: Atmel Corporation

Specifications of R40008

• Flash (kbytes): 0 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 75 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 256
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: No

7. Product Overview
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.5
7.5.1
8
Power Supply
Input/Output Considerations
Master Clock
Reset
Emulation Functions
AT91R40008
NRST Pin
Watchdog Reset
Tri-state Mode
The AT91R40008 microcontroller has two types of power supply pins:
An independent I/O supply allows a flexible adaptation to external component signal levels.
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum
flexibility. It is recommended that in any application phase, the inputs to the AT91R40008
microcontroller be held at valid logic levels to minimize the power consumption.
The AT91R40008 microcontroller has a fully static design and works on the Master Clock
(MCK) provided on the MCKI pin from an external source.
The Master Clock is also provided as an output of the device on the pin MCKO, which is multi-
plexed through a general-purpose I/O line. While NRST is active, MCKO remains low. After
the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO controller must
be programmed to use this pin as standard I/O line.
Reset restores the default states of the user interface registers (defined in the user interface of
each peripheral) and forces the ARM7TDMI to perform the next instruction fetch from address
zero. Except for the program counter, the ARM7TDMI registers do not have defined reset
states.
NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchro-
nized internally to the MCK. The signal presented on MCKI must be active within the
specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct
operation.
The first processor fetch occurs 80 clock cycles after the rising edge of NRST.
The Watchdog can be programmed to generate an internal reset. In this case, the reset has
the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot
Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the Watchdog trig-
gers the internal reset, the NRST pin has priority.
The AT91R40008 microcontroller provides a tri-state mode, which is used for debug purposes.
This enables the connection of an emulator probe to an application board without having to
desolder the device from the target board. In tri-state mode, all the output pin drivers of the
AT91R40008 microcontroller are disabled.
• VDDCORE pins, which power the chip core (i.e., the ARM7TDMI, embedded memory and
• VDDIO pins, which power the I/O lines.
the peripherals).
1732FS–ATARM–12-Apr-06