R40008 Atmel Corporation, R40008 Datasheet - Page 55
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R40008
Manufacturer Part Number
R40008
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.R40008.pdf
(19 pages)
4.R40008.pdf
(20 pages)
Specifications of R40008
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
75 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
256
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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ARM DDI 0029G
System and User
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
CPSR
= banked register
FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq–r14_fiq).
In ARM state, many FIQ handlers do not have to save any registers.
The User, IRQ, Supervisor, Abort, and undefined modes each have two banked registers
mapped to r13 and r14, allowing a private SP and LR for each mode.
System mode shares the same registers as User mode.
Figure 2-3 shows the ARM-state registers.
r0
r1
r2
r3
r4
r5
r6
r7
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r15 (PC)
SPSR_fiq
ARM-state general registers and program counter
Copyright © 1994-2001. All rights reserved.
CPSR
FIQ
ARM-state program status registers
Supervisor
SPSR_svc
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_svc
r14_svc
r15 (PC)
CPSR
Figure 2-3 Register organization in ARM state
SPSR_abt
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_abt
r14_abt
r15 (PC)
CPSR
Abort
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_irq
r14_irq
r15 (PC)
SPSR_irq
CPSR
IRQ
Programmer’s Model
SPSR_und
Undefined
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_und
r14_und
r15 (PC)
CPSR
2-9
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