RM9200 Atmel Corporation, RM9200 Datasheet - Page 28
RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
10.6
10.7
28
SDRAM Controller
Burst Flash Controller
AT91RM9200
• Multiple Wait State Management
• Numerous configurations supported
• Programming facilities
• Energy-saving capabilities
• Error detection
• SDRAM Power-up Initialization by software
• Latency is set to two clocks (CAS Latency of 1, 3 Not Supported)
• Auto Precharge Command not used
• Multiple Access Modes supported
• Adaptability to different device speed grades
• Adaptability to different device access protocols and bus interfaces
– Compliant with LCD Module
– Programmable Setup Time Read/Write
– Programmable Hold Time Read/Write
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Self-refresh and Low-power Modes supported
– Refresh Error Interrupt
– Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses
– Asynchronous Mode Half-word Write Accesses
– Programmable Burst Flash Clock Rate
– Programmable Data Access Time
– Programmable Latency after Output Enable
– Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled
– Multiplexed or separate address and data buses
– Continuous Burst and Page Mode Accesses supported
Address Advance
1768MS–ATARM–09-Jul-09