SAM3N1B Atmel Corporation, SAM3N1B Datasheet - Page 299
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SAM3N1B
Manufacturer Part Number
SAM3N1B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1B
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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19.2.5.3
19.2.5.4
11011A–ATARM–04-Oct-10
Flash Full Erase Command
Flash Lock Commands
Table 19-9.
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command.
However, the lock bit is automatically set at the end of the Flash write operation. As a lock region
is composed of several pages, the programmer writes to the first pages of the lock region using
Flash write commands and writes to the last page of the lock region using a Flash write and lock
command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command.
However, before programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL
commands.
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command.
Otherwise, the erase command is aborted and no page is erased.
Table 19-10. Full Erase Command
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set
Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is pro-
vided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is
activated.
Step
5
6
7
...
n
n+1
n+2
n+3
n+4
n+5
...
Step
1
2
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
...
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Handshake Sequence
Write handshaking
Write handshaking
Write Command (Continued)
MODE[3:0]
ADDR3
DATA
DATA
...
ADDR0
ADDR1
ADDR2
ADDR3
DATA
DATA
...
MODE[3:0]
CMDE
DATA
DATA[7:0]
Memory Address
Memory Address
Memory Address
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
*Memory Address++
*Memory Address++
...
DATA[15:0] or DATA[7:0]
EA
0
SAM3N
299
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