SAM3N1C Atmel Corporation, SAM3N1C Datasheet - Page 72
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SAM3N1C
Manufacturer Part Number
SAM3N1C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.7.3
10.7.4
10.8
72
Power management
SAM3N
Fault status registers and fault address registers
Lockup
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler
executes even though the stack push for the handler failed. The fault handler operates but the
stack contents are corrupted.
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused
the fault, as shown in
Table 10-12. Fault status and fault address registers
The processor enters a lockup state if a hard fault occurs when executing the hard fault han-
dlers. When the processor is in lockup state it does not execute any instructions. The processor
remains in lockup state until:
The Cortex-M3 processor sleep modes reduce power consumption:
Handler
Hard fault
Memory
management fault
Bus fault
Usage fault
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is
• An exception handler causes a fault for which the priority is the same as or lower than the
• A fault occurs and the handler for that fault is not enabled.
• it is reset
• Backup Mode
• Wait Mode
• Sleep Mode
because the handler for the new fault cannot preempt the currently executing fault handler.
currently executing exception.
Status register
name
HFSR
MMFSR
BFSR
UFSR
Table
10-12.
Address register
name
-
MMFAR
BFAR
-
Register description
“Hard Fault Status Register” on page
187
“Memory Management Fault Status
Register” on page 182
“Memory Management Fault Address
Register” on page 188
“Bus Fault Status Register” on page 183
“Bus Fault Address Register” on page
189
“Usage Fault Status Register” on page
185
11011A–ATARM–04-Oct-10
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