SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 47

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SAM3N4A

Manufacturer Part Number
SAM3N4A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N4A

Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6
11.7
11.8
11011AS–ATARM–04-Oct-10
Pulse Width Modulation Controller (PWM)
10-bit Analog-to-Digital Converter
Digital-to-Analog Converter (DAC)
• Two global registers that act on all three TC Channels
• Quadrature decoder
• 2-bit Gray Up/Down Counter for Stepper Motor
• Four channels, one 16-bit counter per channel
• Common clock generator, providing thirteen different clocks
• Independent channel programming
• Up to 16-channel ADC
• 10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register
• ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity
• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger source
• Sleep Mode and conversion sequencer
• 1 channel 10-bit DAC
• Up to 500 ksamples/s conversion rate
• Flexible conversion range
• Multiple trigger sources
• One PDC channel
ADC
– Two multi-purpose input/output signals
– Advanced line filtering
– Position/revolution/speed
– One Modulo n counter providing eleven clocks
– Two independent linear dividers working on modulo n counter outputs
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
SAM3N Summary
47

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