SAM3S1C Atmel Corporation, SAM3S1C Datasheet - Page 48
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SAM3S1C
Manufacturer Part Number
SAM3S1C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S1C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.4.3.8
• ICI
Interruptible-continuable instruction bits, see
• IT
Indicates the execution state bits of the
• T
Always set to 1.
10.4.3.9
10.4.3.10
10.4.3.11
48
SAM3S
Execution Program Status Register
Interruptible-continuable instructions
If-Then block
Exception mask registers
The EPSR contains the Thumb state bit, and the execution state bits for either the:
See the register summary in
ments are:
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the opera-
tion that is at fault. See
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
After servicing the interrupt, the processor:
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruc-
tion in the block is conditional. The conditions for the instructions are either all the same, or
some can be the inverse of others. See
The exception mask registers disable the handling of exceptions by the processor. Disable
exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruc-
tion to change the value of PRIMASK or FAULTMASK. See
144, and
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
• stops the load multiple or store multiple instruction operation temporarily
• stores the next register operand in the multiple operation to EPSR bits[15:12].
• returns to the register pointed to by bits[15:12]
• resumes execution of the multiple load or store instruction.
multiple instruction.
“CPS” on page 139
IT
instruction, see
“Interruptible-continuable instructions” on page
“Exception entry and return” on page 68
for more information.
Table 10-2 on page 44
“IT” on page
“IT” on page 133
133.
for the EPSR attributes. The bit assign-
for more information.
“MRS” on page
48.
143,
6500C–ATARM–8-Feb-11
“MSR” on page
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