SAM3S2B Atmel Corporation, SAM3S2B Datasheet - Page 985
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SAM3S2B
Manufacturer Part Number
SAM3S2B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2B
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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39.6.7
39.6.8
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Comparison Window
Differential Inputs
a Timer/Counter output or the PWM event line. The periodic acquisition of several samples can
be processed automatically without any intervention of the processor thanks to the PDC.
The sequence can be customized by programming the Sequence Channel Registers,
ADC_SEQR1 and ADC_SEQR2 and setting to 1 the USEQ bit of the Mode Register (ADC_MR).
The user can choose a specific order of channels and can program up to 16 conversions by
sequence. The user is totally free to create a personal sequence, by writing channel numbers in
ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be written in any sequence,
channel numbers can be repeated several times. Only enabled sequence bitfields are con-
verted, consequently to program a 15-conversion sequence, the user can simply put a disable in
ADC_CHSR[15], thus disabling the 16THCH field of ADC_SEQR2.
If all ADC channels (i.e. 16) are used on an application board, there is no restriction of usage of
the user sequence. But as soon as some ADC channels are not enabled for conversion but
rather used as pure digital inputs, the respective indexes of these channels cannot be used in
the user sequence fields (ADC_SEQR1, ADC_SEQR2 bitfields). For example, if channel 4 is
disabled (ADC_CSR[4] = 0), ADC_SEQR1, ADC_SEQR2 register bitfields USCH1 up to
USCH16 must not contain the value 4. Thus the length of the user sequence may be limited by
this behavior.
As an example, if only 4 channels over 16 (CH0 up to CH3) are selected for ADC conversions,
the user sequence length cannot exceed 4 channels. Each trigger event may launch up to 4 suc-
cessive conversions of any combination of channels 0 up to 3 but no more (i.e. in this case the
sequence CH0, CH0, CH1, CH1, CH1 is impossible).
A sequence that repeats several times the same channel requires more enabled channels than
channels actually used for conversion. For example, a sequence like CH0, CH0, CH1, CH1
requires 4 enabled channels (4 free channels on application boards) whereas only CH0, CH1
are really converted.
Note:
The ADC Controller features automatic comparison functions. It compares converted values to a
low threshold or a high threshold or both, according to the CMPMODE function chosen in the
Extended Mode Register (ADC_EMR). The comparison can be done on all channels or only on
the channel specified in CMPSEL field of ADC_EMR. To compare all channels the CMP_ALL
parameter of ADC_EMR should be set.
The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trig-
ger an interrupt.
The High Threshold and the Low Threshold can be read/write in the Comparison Window Regis-
ter (ADC_CWR).
The ADC can be used either as a single ended ADC (DIFF bit equal to 0) or as a fully differential
ADC (DIFF bit equal to 1) as shown in
ended mode.
If ANACH is set in ADC_MR the ADC can apply a different mode on each channel. Otherwise
the parameters of CH0 are applied to all channels.
The same inputs are used in single ended or differential mode.
The reference voltage pins always remain connected in normal mode as in sleep mode.
Figure
39-6. By default, after a reset, the ADC is in single
SAM3S
SAM3S
985
985
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