SAM7S128 Atmel Corporation, SAM7S128 Datasheet - Page 107

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SAM7S128

Manufacturer Part Number
SAM7S128
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7S128

Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
19.2.2
Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0
Note:
Figure 19-3. Code Read Optimization in Thumb Mode for FWS = 1
6175L–ATARM–28-Jul-11
ARM Request (16-bit)
ARM Request (16-bit)
Data To ARM
Data To ARM
Buffer (32 bits)
Flash Access
Buffer (32 bits)
Flash Access
Master Clock
Master Clock
Code Fetch
When FWS is equal to 0, all accesses are performed in a single-cycle access.
Code Fetch
Read Operations
@Byte 0
@Byte 0
1 Wait State Cycle
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added
in order to start access at following address during the second read, thus increasing perfor-
mance when the processor is running in Thumb mode (16-bit instruction set). See
Figure 19-3
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be pro-
grammed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see
Flash Mode Register” on page
the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
Bytes 0-3
@Byte 2
Bytes 0-1
Bytes 0-3
and
@Byte 2
Bytes 4-7
@Byte 4
Bytes 0-3
Bytes 2-3
Bytes 0-1
Figure
1 Wait State Cycle
19-4.
Bytes 4-5
@Byte 6
@Byte 4
Bytes 2-3
Bytes 4-7
Bytes 4-7
116). Defining FWS to be 0 enables the single-cycle access of
Bytes 0-3
Bytes 8-11
@Byte 8
@Byte 6
Bytes 6-7
Bytes 4-5
1 Wait State Cycle
@Byte 10
Bytes 8-9
@Byte 8
Bytes 6-7
Bytes 8-11
Bytes 8-11
Bytes 4-7
Bytes 12-15
Bytes 10-11
@Byte 10
@Byte 12
Bytes 8-9
1 Wait State Cycle
SAM7S Series
Bytes 12-13
Bytes 10-11
@Byte 12
@Byte 14
Bytes 12-15
Bytes 8-11
Bytes 12-15
Figure
Bytes 16-19
Bytes 12-13
Bytes 14-15
@Byte 14
@Byte 16
19-2,
“MC
107

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