SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 662
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SAM7S16
Manufacturer Part Number
SAM7S16
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S16
Flash (kbytes)
16 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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40.11.8
40.11.8.1
40.11.8.2
40.11.8.3
40.11.8.4
40.11.8.5
662
SAM7S Series
Serial Peripheral Interface (SPI)
SPI: Bad tx_ready behavior when CSAAT = 1 and SCBR = 1
SPI: LASTXFER (Last Transfer) behavior
SPI: SPCK Behavior in Master Mode
SPI: Chip Select and Fixed Mode
SPI: Baudrate Set to 1
Use RTTINC as an increment for a software counter.
If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed
consecutively on the same slave with an IDLE state between them, the tx_ready signal does not
rise after the second data has been transferred in the shifter. This can imply for example, that
the second data is sent twice.
Do not use the combination CSAAT = 1 and SCBR = 1.
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on
the data written in the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes
a “1” in the bit 24 (LASTXFER bit) of the SPI_TDR, the chip select will rise as soon as the
TXEMPTY flag is set.
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between
transfers.
SPCK pin can toggle out before the first transfer in Master Mode.
Problem Fix/Workaround
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx
registers.
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip
select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Trans-
fer) of SPI_CSR0 register, whatever the selected Chip select is. For example, if SPI_CSR0 is
configured for a 10-bit transfer whereas SPI_CSR1 is configured for an 8-bit transfer, when a
transfer is performed in Fixed mode through the PDC, on Chip select 1, the transfer will be con-
sidered as a HalfWord transfer.
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the
BITS field of the SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of
the CSRy Register.
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency)
and when the BITS field of the SPI_CSR register (number of bits to be transmitted) equals an
ODD value (in this case 9,11,13 or 15), an additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
None.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6175L–ATARM–28-Jul-11
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