SAM7S321 Atmel Corporation, SAM7S321 Datasheet - Page 94
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SAM7S321
Manufacturer Part Number
SAM7S321
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S321
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Interface
3.6.2
3.6.3
3-24
ABORT
Byte latch enables
ABORT indicates that a memory transaction failed to complete successfully. ABORT
is sampled at the end of the bus cycle during S-cycles and N-cycles.
If ABORT is asserted on a data access, it causes the processor to take the Data Abort
trap. If it is asserted on an opcode fetch, the abort is tracked down the pipeline, and the
Prefetch Abort trap is taken if the instruction is executed.
ABORT can be used by a memory management system to implement, for example, a
basic memory protection scheme, or a demand-paged virtual memory system.
To ease the connection of the ARM7TDMI core to sub-word sized memory systems,
input data and instructions can be latched on a byte-by-byte basis. This is achieved by
the use of the BL[3:0] signal as follows:
•
•
•
•
It is recommended that BL[3:0] is tied HIGH in new designs and word values from
narrow memory systems are latched onto latches that are external to the ARM7TDMI
core.
In a memory system that only contains word-wide memory, BL[3:0] can be tied HIGH.
For sub-word wide memory systems, the BL[3:0] signals are used to latch the data as it
is read out of memory. For example, a word access to halfword wide memory must take
place in two memory cycles:
•
•
In Figure 3-18 on page 3-25, a word access is performed from halfword wide memory
in two cycles:
•
•
BL[3] controls the latching of the data present on D[31:24]
BL[2] controls the latching of the data present on D[23:16]
BL[1] controls the latching of the data present on D[15:8]
BL[0] controls the latching of the data present on D[7:0].
in the first cycle, the data for D[15:0] is obtained from the memory and latched
into the core on the falling edge of MCLK when BL[1:0] are both HIGH.
in the second cycle, the data for D[31:16] is latched into the core on the falling
edge of MCLK when BL[3:2] are both HIGH and BL[1:0] are both LOW.
in the first cycle, the read data is applied to the lower half of the bus
in the second cycle, the read data is applied to the upper half of the bus.
Note
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G
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