SAM7SE32 Atmel Corporation, SAM7SE32 Datasheet - Page 204

• Manufacturer Part Number: SAM7SE32
• Manufacturer: Atmel Corporation

Specifications of SAM7SE32

• Flash (kbytes): 32 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.6
23.6.1
Figure 23-3. Write Burst, 32-bit SDRAM Access
204
D[31:0]
A[12:0]
SDWE
SDCS
SDCK
RAS
CAS
Functional Description
SAM7SE512/256/32
SDRAM Controller Write Cycle
Row n
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the transfer type signal provided by the master requesting the access. If
the next access is a sequential write access, writing to the SDRAM device is carried out. If the
next access is a write-sequential access, but the current access is to a boundary page, or if the
next access is in another row, then the SDRAM Controller generates a precharge command,
activates the new row and initiates a write command. To comply with SDRAM timing parameters,
additional clock cycles are inserted between precharge/active (t
(t
Register” on page
t
RCD
RCD
) commands. For definition of these timing parameters, refer to the
= 3
col a
Dna
213. This is described in
col b
Dnb
col c
Dnc
col d
Dnd
col e
Dne
Figure 23-3
col f
Dnf
col g
Dng
below.
col h
Dnh
RP
col i
Dni
) commands and active/write
“SDRAMC Configuration
col j
Dnj
6222F–ATARM–14-Jan-11
col k
Dnk
col l
Dnl