SAM7SE512 Atmel Corporation, SAM7SE512 Datasheet - Page 655

• Manufacturer Part Number: SAM7SE512
• Manufacturer: Atmel Corporation

Specifications of SAM7SE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

43.2.5
43.2.5.1
43.2.6
43.2.6.1
43.2.6.2
43.2.6.3
6222F–ATARM–14-Jan-11
SDRAM Controller (SDRAMC)
Serial Peripheral Interface (SPI)
SPI: Baudrate Set to 1
SPI: Bad Serial Clock Generation on 2nd Chip Select
SDRAMC: PDC Buffer in 16-bit SDRAM while the Core Accesses SDRAM
SPI: Software Reset Must Be Written Twice
The software must handle RTT event as interrupt and should not poll RTT_SR.
When the SAM7SE interfaces with 16-bit SDRAM memory and the processor accesses the
SDRAM, either for instruction fetch or data read/write, the data transferred by the PDC from
SDRAM buffers to the peripherals might be corrupted. Transfers from peripherals to SDRAM
buffers are not affected.
Map the transmit PDC buffers in internal SRAM or Flash.
When the Baudrate is set at 1 (so, the serial clock frequency equals the master clock), and when
the BITS field (number of bits to be transmitted) in SPI_CSRx equals an odd value (in this case
9, 11, 13 or 15), an additional pulse will be generated on SPCK.
It does not occur when the BITS field is equal to 8, 10, 12, 14 or 16 and the Baudrate is equal
to 1.
None.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop-
erly (the clock is enabled before the chip select).
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly
set.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SAM7SE512/256/32
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