SAM7SE512 Atmel Corporation, SAM7SE512 Datasheet - Page 230

• Manufacturer Part Number: SAM7SE512
• Manufacturer: Atmel Corporation

Specifications of SAM7SE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B.5.8
B.5.9
B.5.10 BYPASS (1111)
B-12
INTEST (1100)
IDCODE (1110)
The INTEST instruction places the selected scan chain in test mode:
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Single-step operation of the core is possible using the INTEST instruction.
The IDCODE instruction connects the device identification code register or ID register
between TDI and TDO. The register is a 32-bit register that enables the manufacturer,
part number, and version of a component to be read through the TAP. See ARM7TDMI
core device IDentification (ID) code register on page B-14 for details of the ID register
format.
When the IDCODE instruction is loaded into the instruction register, all the scan cells
are placed in their normal system mode of operation:
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The BYPASS instruction connects a 1-bit shift register, the bypass register, between
TDI and TDO.
The INTEST instruction connects the selected scan chain between TDI and TDO.
When the INTEST instruction is loaded into the instruction register, all the scan
cells are placed in their test mode of operation.
In the CAPTURE-DR state, the value of the data applied from the core logic to
the output scan cells and the value of the data applied from the system logic to the
input scan cells is captured.
In the SHIFT-DR state, the previously-captured test data is shifted out of the scan
chain through the TDO pin, while new test data is shifted in through the TDI pin.
In the CAPTURE-DR state, the device identification code is captured by the ID
register.
In the SHIFT-DR state, the previously captured device identification code is
shifted out of the ID register through the TDO pin, while data is shifted into the
ID register through the TDI pin.
In the UPDATE-DR state, the ID register is unaffected.
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ARM DDI 0029G