SAM7XC128 Atmel Corporation, SAM7XC128 Datasheet - Page 68
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SAM7XC128
Manufacturer Part Number
SAM7XC128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
32
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Programmer’s Model
2.8.10
2-22
Exception priorities
Address
When multiple exceptions arise at the same time, a fixed priority system determines the
order in which they are handled. The priority order is listed in Table 2-5.
Some exceptions cannot occur together:
•
•
The undefined instruction and SWI exceptions are mutually exclusive. Each
corresponds to a particular, non-overlapping, decoding of the current instruction.
When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the
ARM7TDMI processor enters the Data Abort handler, and proceeds immediately
to the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Data Aborts must have higher priority than FIQs to ensure that the transfer error
does not escape detection. You must add the time for this exception entry to the
worst-case FIQ latency calculations in a system that uses aborts to support virtual
memory.
Exception
Data Abort
Reserved
IRQ
FIQ
Copyright © 1994-2001. All rights reserved.
Mode on entry
Abort
Reserved
IRQ
FIQ
Priority
Highest
Lowest
Table 2-4 Exception vectors (continued)
I state on entry
Set
-
Set
Set
Table 2-5 Exception priority order
Exception
Reset
Data Abort
FIQ
IRQ
Prefetch Abort
Undefined instruction and SWI
F state on entry
Unchanged
-
Unchanged
Set
ARM DDI 0029G
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