SAM9G35 Atmel Corporation, SAM9G35 Datasheet - Page 142
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SAM9G35
Manufacturer Part Number
SAM9G35
Description
Manufacturer
Atmel Corporation
Specifications of SAM9G35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Bus Interface Unit
6.1
6-2
About the bus interface unit
The ARM926EJ-S Bus Interface Unit (BIU) arbitrates and schedules AHB requests.
The BIU contains separate masters for both instruction and data access enabling
complete AHB system flexibility. Separate masters enable multi-layer AHB (see the
Multi-layer AHB Overview) and multi-AHB systems to be implemented, giving the
benefit of increased overall bus bandwidth and a more flexible system architecture.
Each master is a fully compliant AHB bus master and implements the master functions
as defined in the AMBA Specification (Rev 2.0).
To increase system performance, write buffers are used to prevent AHB writes stalling
the ARM926EJ-S system. For more details, see Chapter 4 Caches and Write Buffer.
The data BIU AHB signals are prefixed with D, and the instruction BIU signals are
prefixed with I.
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
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