SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 5

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.7
2.7.1
2.8
2.8.1
2.9
2.9.1
2.9.2
2.9.3
6485B–ATARM–28-Sep-09
Pulse Width Modulation Controller (PWM)
Reset Controller (RSTC)
Serial Synchronous Controller (SSC)
PWM: Zero Period
RSTC: NRST Signal, input mode not available at startup
SSC: Clock is Transmitted before the SSC is enabled
SSC: Last RK Clock Cycle when RK Outputs a Clock during data transfer
SSC: First RK Clock Cycle when RK Outputs a Clock during data transfer
It is impossible to update a period equal to 0 by using the PWM_CUPD register.
None
The NRST input mode power-up is not available at reset. The NRST mode is output at power-
up.
None
SSC configuration:
=> the clock is transmitted.
Configure PIO lines for SSC usage after first enabling the SSC.
When the SSC receiver is used with the following conditions:
At the end of the data cycle, the RK pin is set in high impedance which might be seen as an
unexpected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK /(2 x (value +1)).
• Performs a SW reset,
• Program the receive and the transmit frame synchro,
• Program the transmit and the receive clock as continuous (CKO = Continuous Receive and
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
Transmit Clock)
Problem/Fix Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9G45 Errata
5