SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 51

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

10.16 True Random Number Generator (TRNG)
10.17 Video Decoder (VDEC)
6355DS–ATARM–7-Sep-11
Decoder supported standards:
Post-processor features:
• Channel Control
• Transfer Initiation
• Interrupt
• Passed NIST Special Publication 800-22 Tests Suite
• Passed Diehard Random Tests Suite
• Provides a 32-bit Random Number Every 84 Clock Cycles
• For 133 MHz Clock Frequency, Throughput Close to 50 Mbits/s
• Little-endian and Big-endian support.
• MPEG-4 Simple and Advanced Profile, levels 0-5
• H.264 Baseline Profile, levels 1-3.1
• H.263 Profile 0, levels 10-70
• VC-1
• MPEG-2 Main Profile, Low, Medium and High Levels
• JPEG Profile Baseline DCT (sequential) and JFIF 1.02 file form
• Image up-scaling
• Image down-scaling
• YCbCr to RGB conversion
• Dithering
• Deinterlacing
• Programmable alpha channel
• Alpha blending
• De-blocking filter for MPEG-4 simple profile/H.263
– 16-word FIFO
– Automatic packing/unpacking of data to fit FIFO width
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
– Support for Software handshaking interface. Memory mapped registers can be used
– Programmable Interrupt generation on DMA Transfer completion Block Transfer
– Simple Profile, Low and Medium Levels
– Main Profile, Low, Medium and High Levels
– Advanced Profile, Levels 0-3
to control the flow of a DMA transfer in place of a hardware handshaking interface
completion, Single/Multiple transaction completion or Error condition
SAM9M10
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